ZHCSF07A March 2016 – January 2017 TLV62095
PRODUCTION DATA.
- 1 特性
- 2 應用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
10 Layout
10.1 Layout Guidelines
- It is recommended to place the input capacitor as close as possible to the IC pins PVIN and PGND.
- The VOS connection is noise sensitive and needs to be routed short and direct to the output terminal of the inductor.
- The exposed thermal pad of the package, analog ground (pin 6) and power ground (pin 14, 15) should have a single point connection at the exposed thermal pad of the package. This minimizes switch node jitter.
- The charge pump capacitor connected to CP and CN should be placed close to the IC to minimize coupling of switching waveforms into other traces and circuits.
- Refer to Figure 23 for an example of component placement, routing and thermal design.
10.2 Layout Example
Figure 23. TLV62095 PCB Layout
10.3 Thermal Consideration
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. The Thermal Information table provides the thermal metric of the device and its package based on JEDEC standard. For more details on how to use the thermal parameters in real applications, see the application notes: SZZA017 and SPRA953.