Configure the circuit as shown in GUID-71B8BF3B-402C-47F3-85E6-496EB22FE5A0.html#SLVSCI74383. Connect (V+) to 3.3 V which also powers the micro-controller. Resistors R₁ and R₂ create the under-voltage alert level of 2.0 V. When the battery voltage sags down to 2.0 V, the resistor divider voltage crosses the (V_IT-) threshold of the TLV4041R1. This causes the comparator output to transition from a logic high to a logic low. The push-pull option of the TLV40x1 family is selected since the comparator operating voltage is shared with the microcontroller which is receiving the under-voltage alert signal. The TLV4041 option with the 1.2 V internal reference is selected because it is the closest internal reference option that is less than the critical under-voltage level of 2.0 V. Choosing the internal reference option that is closest to the critical under-voltage level minimizes the resistor divider ratio which optimizes the accuracy of the circuit. Error at the falling edge threshold of (V_IT-) is amplified by the inverse of the resistor divider ratio. So minimizing the resistor divider ratio is a way of optimizing voltage monitoring accuracy.

#SBVS2501082 is derived from the analysis of GUID-71B8BF3B-402C-47F3-85E6-496EB22FE5A0.html#SLVSCI74383.

Equation 1.

where

• R₁ and R₂ are the resistor values for the resistor divider connected to IN
• V_BAT is the voltage source that is being monitored for an undervoltage condition.
• V_IT- is the falling edge threshold where the comparator output changes state from high to low

Rearranging #SBVS2501082 and solving for R₁ yields #SNVSB044925.

Equation 2.

For the specific undervoltage detection of 2.0 V using the TLV4041R1, the following results are calculated.

Equation 3.

where

• R₂ is set to 1 MΩ
• V_BAT is set to 2.0 V
• V_IT- is set to1.18 V

Choose R_TOTAL (R₁ + R₂) such that the current through the divider is at least 100 times higher than the input bias current (I_BIAS). The resistors can have high values to minimize current consumption in the circuit without adding significant error to the resistive divider.