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ZHCSIV8B January 2010 – October 2018 TLV320DAC3101

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RHB|32
- MPQF130D

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RHB|32
- QFND029X

訂購信息

6.3.11 CLOCK Generation and PLL

The device supports a wide range of options for generating clocks for the DAC section as well as interface and other control blocks as shown in Figure 6-19. The clocks for the DAC require a source reference clock. This clock is provided on a variety of device pins, such as the MCLK, BCLK, or GPIO1 pins. The source reference clock for the codec is chosen by programming the CODEC_CLKIN value on page 0 / register 4, bits D1–D0. The CODEC_CLKIN is then routed through highly-flexible clock dividers shown in Figure 6-19 to generate the various clocks required for the DAC. In the event that the desired audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO1, the device also provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN, the device provides several programmable clock dividers to help achieve a variety of sampling rates for the DAC.

Figure 6-19 Clock Distribution Tree

Equation 5. TLV320DAC3101 eq_5-8_las659.gif

Table 6-26 CODEC CLKIN Clock Dividers

DIVIDER	BITS
NDAC	Page 0 / register 11, bits D6–D0
MDAC	Page 0 / register 12, bits D6–D0
DOSR	Page 0 / register 13, bits D1–D0 and page 0 / register 14, bits D7–D0

The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel, DAC_MOD_CLK must be enabled by configuring the NDAC and MDAC clock dividers (page 0 / register 11, bit D7 = 1 and page 0 / register 12, bit D7 = 1). When the DAC channel is powered down, the device internally initiates a power-down sequence for proper shutdown. During this shutdown sequence, the NDAC and MDAC dividers must not be powered down, or else a proper low-power shutdown may not take place. The user can read back the power-status flag at page 0 / register 37, bit D7 and page 0 / register 37, bit D3. When both of the flags indicate power-down, the MDAC divider may be powered down, followed by the NDAC divider.

In general, for proper operation, all the root clock dividers must power down only after the child clock dividers have powered down.

The device also has options for routing some of the internal clocks to the GPIO1 pin to be used as general-purpose clocks in the system. The feature is shown in Figure 6-21.

Figure 6-20 BCLK Output Options

In the mode when the device is configured to drive the BCLK pin (page 0 / register 27, bit D3 = 1), the device is driven as the divided value of BDIV_CLKIN. The division value is programmed in page 0 / register 30, bits D6–D0 from 1 to 128. The BDIV_CLKIN is configurable to be one of DAC_CLK (DAC processing clock) or DAC_MOD_CLK by configuring the BDIV_CLKIN multiplexer in page 0 / register 29, bits D1–D0. Additionally, a general-purpose clock can be driven out on GPIO1.

This clock can be a divided-down version of CDIV_CLKIN. The value of this clock divider can be programmed from 1 to 128 by writing to page 0 / register 26, bits D6–D0. CDIV_CLKIN can also be programmed as one of the clocks among the list shown in Figure 6-21. This is controlled by programming the multiplexer in page 0 / register 25, bits D2–D0.

Figure 6-21 General-Purpose Clock Output Options

Table 6-27 Maximum Clock Frequencies

CLOCK	DVDD ≥ 1.65 V
CODEC_CLKIN	≤ 110 MHz
DAC_CLK (DAC processing clock)	≤ 49.152 MHz
DAC_MOD_CLK	≤ 49.152 MHz with DRC disabled ≤ 48 MHz with DRC enabled
DAC_MOD_CLK	6.758 MHz
DAC_f_S	0.192 MHz
BDIV_CLKIN	55 MHz
CDIV_CLKIN	100 MHz when M is odd 110 MHz when M is even