亚洲国产精品自在拍在线播放蜜臀,精品一区二区无码AV,日韩精品一区二区三区久久久

ZHCSIV8B January 2010 – October 2018 TLV320DAC3101

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RHB|32
- MPQF130D

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RHB|32
- QFND029X

訂購(gòu)信息

6.3.10.1.3 DAC User-Programmable Filters

Based on the selected processing block, different types and orders of digital filtering are available. Up to six biquad sections are available for specific processing blocks.

The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If adaptive filtering is chosen, the coefficient banks can be switched in real time.

When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed for either read or write.

However, the device offers an adaptive filter mode as well. Setting page 8 / register 1, bit D2 = 1 turns on double buffering of the coefficients. In this mode, filter coefficients are updated through the host and activated without stopping and restarting the DAC which enables advanced adaptive filtering applications.

In the double-buffering scheme, all coefficients are stored in two buffers (buffers A and B). When the DAC is running and the adaptive filtering mode is turned on, setting page 8 / register 1, bit D0 = 1 switches the coefficient buffers at the next start of a sampling period. This bit is set back to 0 after the switch occurs. At the same time, page 8 / register 1, bit D1 toggles.

The flag in page 8 / register 1, bit D1 indicates which of the two buffers is actually in use.

Page 8 / register 1, bit D1 = 0: buffer A is in use by the DAC processing block; bit D1 = 1: buffer B is in use.

While the device is running, coefficient updates are always made to the buffer not in use by the DAC, regardless of the buffer to which the coefficients have been written.

Table 6-12 Adaptive-Mode Filter-Coefficient Buffer Switching

DAC POWERED UP	PAGE 8 / REGISTER 1, BIT D1	COEFFICIENT BUFFER IN USE	WRITING TO	UPDATES
No	0	None	Buffer A (Pages 8 and 9)	Buffer A (Pages 8 and 9)
No	0	None	Buffer B (Pages 12 and 13)	Buffer B (Pages 12 and 13)
Yes	0	Buffer A	Buffer A (Pages 8 and 9)	Buffer B (Pages 12 and 13)
Yes	0	Buffer A	Buffer B (Pages 12 and 13)	Buffer B (Pages 12 and 13)
Yes	1	Buffer B	Buffer A (Pages 8 and 9)	Buffer A (Pages 8 and 9)
Yes	1	Buffer B	Buffer B (Pages 12 and 13)	Buffer A (Pages 8 and 9)

The user-programmable coefficients for the DAC processing blocks are defined on pages 8 and 9 for buffer A and pages 12 and 13 for buffer B.

The coefficients of these filters are each 16-bit, 2s-complement format, occupying two consecutive 8-bit registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF) as shown in Figure 6-12.

Figure 6-12 1.15 2s-Complement Coefficient Format