10.3.1 Device Connections

10.3.2 Analog Audio IO

10.3.3 ADC

The TLV320AIC3254 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable oversampling ratio, followed by a digital decimation filter. The ADC supports sampling rates from 8kHz to 192kHz. In order to provide optimal system power management, the stereo recording path can be powered up one channel at a time, to support the case where only mono record capability is required.

The ADC path of the TLV320AIC3254 features a large set of options for signal conditioning as well as signal routing:

• Two ADCs
• Six analog inputs which can be mixed and-or multiplexed in single-ended and-or differential configuration
• Two programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
• Two mixer amplifiers for analog bypass
• Two low power analog bypass channels
• Fine gain adjustment of digital channels with 0.1dB step size
• Digital volume control with a range of -12 to +20dB
• Mute function
• Automatic gain control (AGC)

In addition to the standard set of ADC features the TLV320AIC3254 also offers the following special functions:

• Built in microphone bias
• Stereo digital microphone interface
• Channel-to-channel phase adjustment
• Fast charge of ac-coupling capacitors
• Anti thump
• Adaptive filter mode

For more detailed information see the TLV320AIC3254 Application Reference Guide,SLAA408.

10.3.4 DAC

The TLV320AIC3254 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a programmable miniDSP, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20kHz. To handle multiple input rates and optimize power dissipation and performance, the TLV320AIC3254 allows the system designer to program the oversampling rates over a wide range from 1 to 1024. The system designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data rates.

The TLV320AIC3254 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on required frequency response, group delay and sampling rate.

The DAC path of the TLV320AIC3254 features many options for signal conditioning and signal routing:

• 2 headphone amplifiers
  • Usable in single-ended or differential mode
  • Analog volume setting with a range of -6 to +29dB
  • Class-D mode
• 2 line-out amplifiers
  • Usable in single-ended or differential mode
  • Analog volume setting with a range of -6 to +29dB
• Digital volume control with a range of -63.5 to +24dB
• Mute function
• Dynamic range compression (DRC)

In addition to the standard set of DAC features the TLV320AIC3254 also offers the following special features:

• Built in sine wave generation (beep generator)
• Digital auto mute
• Adaptive filter mode

For more detailed information see the TLV320AIC3254 Application Reference Guide,SLAA408.

10.3.5 PowerTune

The TLV320AIC3254 features PowerTune, a mechanism to balance power-versus-performance trade-offs at the time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance, or to an operating point between the two extremes to best fit the application. The TLV320AIC3254 PowerTune modes are called PTM_R1 to PTM_R4 for the recording (ADC) path and PTM_P1 to PTM_P4 for the playback (DAC) path.

For more detailed information see the TLV320AIC3254 Application Reference Guide,SLAA408.

10.3.6 Digital Audio IO Interface

Audio data flows between the host processor and the TLV320AIC3254 on the digital audio data serial interface, or audio bus. This very flexible bus includes left or right-justified data options, support for I²S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master-slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly.

The audio bus of the TLV320AIC3254 can be configured for left or right-justified, I²S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Page 0, Register 27, D(5:4). In addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.

The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0, Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various word lengths, and to support the case when multiple TLV320AIC3254s may share the same audio bus.

The TLV320AIC3254 also includes a feature to offset the position of start of data transfer with respect to the word-clock. Control the offset in terms of number of bit-clocks by programming Page 0, Register 28.

The TLV320AIC3254 also has the feature to invert the polarity of the bit-clock used to transfer the audio data as compared to the default clock polarity used. This feature can be used independently of the mode of audio interface chosen. Page 0, Register 29, D(3) configures bit clock polarity.

The TLV320AIC3254 further includes programmability (Page 0, Register 27, D(0)) to place the DOUT line into a hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z output condition.

By default when the word-clocks and bit-clocks are generated by the TLV320AIC3254, these clocks are active only when the codec (ADC, DAC or both) are powered up within the device. This intermittent clock operation reduces power consumption. However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec in the device is powered down. This continuous clock feature is useful when using the TDM mode with multiple codecs on the same bus, or when word-clock or bit-clocks are used in the system as general-purpose clocks.

10.3.7 Clock Generation and PLL

The TLV320AIC3254 supports a wide range of options for generating clocks for the ADC and DAC sections as well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the miniDSP sections. In the event that the desired audio or miniDSP clocks cannot be generated from the reference clocks on MCLK BCLK or GPIO, the TLV320AIC3254 also provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN the TLV320AIC3254 provides several programmable clock dividers to help achieve a variety of sampling rates for ADC, DAC and clocks for the miniDSP.

To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required internal clock signals at very low power consumption. For cases where such master clocks are not available, the built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL is used to generate some other clock that is only used outside the TLV320AIC3254.

For more detailed information see the TLV320AIC3254 Application Reference Guide,SLAA408.

10.3.8 Control Interfaces

The TLV320AIC3254 control interface supports SPI or I²C communication protocols, with the protocol selectable using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I²C, SPI_SELECT should be tied low. Changing the state of SPI_SELECT during device operation is not recommended.

For more detailed information see the TLV320AIC3254 Application Reference Guide,SLAA408.

Table 4. Summary of Register Map