7.14 DSP Timing in Master Mode (see Figure 3)
|
IOVDD = 1.8V |
IOVDD = 3.3V |
UNIT |
| MIN |
MAX |
MIN |
MAX |
| td(WS) |
WCLK delay |
|
30 |
|
20 |
ns |
| td(DO-BCLK) |
BCLK to DOUT delay |
|
22 |
|
20 |
ns |
| ts(DI) |
DIN setup |
8 |
|
8 |
|
ns |
| th(DI) |
DIN hold |
8 |
|
8 |
|
ns |
| tr |
BCLK rise time |
|
24 |
|
12 |
ns |
| tf |
BCLK fall time |
|
24 |
|
12 |
ns |