SLAS663C August 2009 – June 2016 TLV320AIC3106-Q1
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Description (Continued)
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
-
8 Specifications
- 8.1 Absolute Maximum Ratings
- 8.2 ESD Ratings
- 8.3 Recommended Operating Conditions
- 8.4 Thermal Information
- 8.5 Electrical Characteristics
- 8.6 Switching Characteristics I2S/LJF/RJF In Master Mode
- 8.7 Switching Characteristics I2S/LJF/RJF In Slave Mode
- 8.8 Switching Characteristics DSP In Master Mode
- 8.9 Switching Characteristics DSP In Slave Mode
- 8.10 Typical Characteristics
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Audio Data Converters
- 9.3.2 Stereo Audio ADC
- 9.3.3 Automatic Gain Control (AGC)
- 9.3.4 Stereo Audio DAC
- 9.3.5 Digital Audio Processing For Playback
- 9.3.6 Digital Interpolation Filter
- 9.3.7 Delta-Sigma Audio Dac
- 9.3.8 Audio Dac Digital Volume Control
- 9.3.9 Analog Output Common-Mode Adjustment
- 9.3.10 Audio DAC Power Control
- 9.3.11 Audio Analog Inputs
- 9.3.12 Analog Input Bypass Path Functionality
- 9.3.13 ADC PGA Signal Bypass Path Functionality
- 9.3.14 Input Impedance and VCM Control
- 9.3.15 MICBIAS Generation
- 9.3.16 Analog Fully Differential Line Output Drivers
- 9.3.17 Analog High Power Output Drivers
- 9.3.18 Short Circuit Output Protection
- 9.3.19 Jack and Headset Detection
- 9.3.20 General-Purpose I/O
- 9.4 Device Functional Modes
- 9.5
Programming
- 9.5.1 Hardware Reset
- 9.5.2 Digital Control Serial Interface
- 9.5.3 I2C Control Mode
- 9.5.4 I2C Bus Debug In A Glitched System
- 9.5.5 Digital Audio Data Serial Interface
- 9.5.6 Right-Justified Mode
- 9.5.7 Left-Justified Mode
- 9.5.8 I2S Mode
- 9.5.9 DSP Mode
- 9.5.10 TDM Data Transfer
- 9.5.11 Audio Clock Generation
- 9.6 Register Maps
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, And Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
訂購信息
8 Specifications
8.1 Absolute Maximum Ratings
see (1)| MIN | MAX | UNIT | |
|---|---|---|---|
| AVDD_DAC to AVSS_DAC, DRVDD to DRVSS, AVSS_ADC | –0.3 | 3.9 | V |
| AVDD to DRVSS | –0.3 | 3.9 | V |
| IOVDD to DVSS | –0.3 | 3.9 | V |
| DVDD to DVSS | –0.3 | 2.5 | V |
| AVDD_DAC to DRVDD | –0.1 | 0.1 | V |
| Digital input voltage to DVSS | –0.3 | VIOVDD + 0.3 | V |
| Analog input voltage to AVSS_ADC | –0.3 | VAVDD + 0.3 | V |
| Power dissipation | (TJ(MAX) – TA) / θJA | ||
| Operating temperature range | –40 | 85 | °C |
| Junction temperature, TJ | 105 | °C | |
| Storage temperature, Tstg | –65 | 105 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±1500 | V |
| Charged-device model (CDM), per AEC Q100-011 | ±1000 | |||
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VAVDD_DAC, VDRVDD | Analog supply voltage(1) | 2.7 | 3.3 | 3.6 | V |
| VDVDD | Digital core supply voltage(1) | 1.65 | 1.8 | 1.95 | V |
| VIOVDD | Digital I/O supply voltage(1) | 1.1 | 1.8 | 3.6 | V |
| VI | Analog, full-scale, 0-dB input voltage (DRVDD1 = 3.3 V) | 0.707 | VRMS | ||
| Stereo line output load resistance | 10 | kΩ | |||
| Stereo headphone output load resistance | 16 | Ω | |||
| Digital output load capacitance | 10 | pF | |||
| TA | Operating free-air temperature | –40 | 85 | °C | |
(1) Analog voltage values are with respect to AVSS_ADC, AVSS_DAC, DRVSS; digital voltage values are with respect to DVSS.
8.4 Thermal Information
| THERMAL METRIC(1) | TLV320AIC3106-Q1 | UNIT | |
|---|---|---|---|
| RGZ (VQFN) | |||
| 48 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 30.7 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 13.4 | °C/W |
| RθJB | Junction-to-board thermal resistance | 7.2 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
| ψJB | Junction-to-board characterization parameter | 7.2 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.5 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
8.5 Electrical Characteristics
TA = –40°C to 85°C, VAVDD_DAC, VDRVDD, VIOVDD = 3.3 V, VDVDD = 1.8 V, fS = 48-kHz, 16-bit audio data(unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| AUDIO ADC | ||||||
| Input signal level (0 dB) | Single-ended input | 0.707 | VRMS | |||
| Signal-to-noise ratio, A-weighted(1)(2) | fS = 48 ksps, 0-dB PGA gain, inputs AC-shorted to ground | 80 | 92 | dB | ||
| Dynamic range(2) | fS = 48 ksps, 0-dB PGA gain, –60-dB full-scale input signal | 91 | dB | |||
| THD | Total harmonic distortion | fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale, 1-kHz input signal |
–88 | –70 | dB | |
| PSRR | Power supply rejection ratio | 217-Hz signal applied to DRVDD | 49 | dB | ||
| 1-kHz signal applied to DRVDD | 46 | |||||
| Gain error | fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale, 1-kHz input signal |
0.84 | dB | |||
| Input channel separation | 1-kHz, –2-dB full-scale signal, MIC3L to MIC3R | –86 | dB | |||
| 1-kHz, –2-dB full-scale signal, MIC2L to MIC2R | –98 | |||||
| 1-kHz, –2-dB full-scale signal, MIC1L to MIC1R | –75 | |||||
| ADC programmable gain amplifier maximum gain | 1-kHz input tone | 59.5 | dB | |||
| ADC programmable gain amplifier step size | 0.5 | dB | ||||
| Input resistance | MIC1L and MIC1R inputs routed to single ADC, Input mix attenuation = 0 dB |
20 | kΩ | |||
| MIC1L and MIC1R inputs routed to single ADC, input mix attenuation = 12 dB |
80 | |||||
| MIC2L and MIC2R inputs routed to single ADC, Input mix attenuation = 0 dB |
20 | |||||
| MIC2L and MIC2R inputs routed to single ADC, input mix attenuation = 12 dB |
80 | |||||
| MIC3L and MIC3R inputs routed to single ADC, Input mix attenuation = 0 dB |
20 | |||||
| MIC3L and MIC3R inputs routed to single ADC, input mix attenuation = 12 dB |
80 | |||||
| Input level control minimum attenuation setting | 0 | dB | ||||
| Input level control maximum attenuation setting | 12 | dB | ||||
| Input signal level | Differential Input | 1.414 | VRMS | |||
| Signal-to-noise ratio, A-weighted(1)(2) | fS = 48 ksps, 0-dB PGA gain, inputs AC-shorted to ground, differential mode | 92 | dB | |||
| THD | Total harmonic distortion | fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale 1-kHz input signal, differential mode |
–91 | dB | ||
| ANALOG PASS THROUGH MODE | ||||||
| Input to output switch resistance, (rDS(ON)) | MIC1/LINE1 to LINE_OUT | 330 | Ω | |||
| MIC2/LINE2 to LINE_OUT | 330 | |||||
| ADC DIGITAL DECIMATION FILTER, fS = 48 kHz | ||||||
| Filter gain from 0 to 0.39 fS | ±0.1 | dB | ||||
| Filter gain at 0.4125 fS | –0.25 | dB | ||||
| Filter gain at 0.45 fS | –3 | dB | ||||
| Filter gain at 0.5 fS | –17.5 | dB | ||||
| Filter gain from 0.55 fS to 64 fS | –75 | dB | ||||
| Filter group delay | 17 / fS | s | ||||
| MICROPHONE BIAS | ||||||
| Bias voltage | Programmable setting = 2 | 2 | V | |||
| Programmable setting = 2.5 | 2.3 | 2.5 | 2.7 | |||
| Programmable setting = VDRVDD | VDRVDD | |||||
| Current sourcing | Programmable setting = 2.5 V | 4 | mA | |||
| AUDIO DAC: DIFFERENTIAL LINE OUTPUT, LOAD = 10 kΩ | ||||||
| Full-scale output voltage | 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V | 1.414 | VRMS | |||
| SNR | Signal-to-noise ratio, A-weighted(3) | No input signal, output volume control = 0 dB, output common mode setting = 1.35 V, fS = 48 kHz |
90 | 102 | dB | |
| Dynamic range, A-weighted | –60-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
99 | dB | |||
| THD | Total harmonic distortion | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
–94 | –75 | dB | |
| Power-supply rejection ratio | 217-Hz signal applied to DRVDD, AVDD_DAC | 77 | dB | |||
| 1-kHz signal applied to DRVDD, AVDD_DAC | 73 | |||||
| DAC channel separation | 0-dB full-scale input signal between left and right line out | 123 | dB | |||
| DAC gain error | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
–0.4 | dB | |||
| AUDIO DAC: SINGLE ENDED LINE OUTPUT, LOAD = 10 kΩ | ||||||
| Full-scale output voltage | 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V | 0.707 | Vrms | |||
| SNR | Signal-to-noise ratio, A-weighted | No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
97 | dB | ||
| THD | Total harmonic distortion | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
84 | dB | ||
| DAC gain error | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
0.55 | dB | |||
| AUDIO DAC: SINGLE ENDED HEADPHONE OUTPUT, LOAD = 16 Ω | ||||||
| Full-scale output voltage | 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V | 0.707 | Vrms | |||
| SNR | Signal-to-noise ratio, A-weighted | No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
95 | dB | ||
| No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, 50% DAC current boost mode |
96 | dB | ||||
| Dynamic range, A-weighted | –60-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
92 | dB | |||
| THD | Total harmonic distortion | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, 25°C |
–80 | –65 | dB | |
| PSRR | Power-supply rejection ratio | 217-Hz signal applied to DRVDD, AVDD_DAC | 41 | dB | ||
| 1-kHz signal applied to DRVDD, AVDD_DAC | 44 | |||||
| DAC channel separation | 0-dB full-scale input signal between left and right line out | 84 | dB | |||
| DAC gain error | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz |
–0.5 | dB | |||
| AUDIO DAC: LINEOUT AND HEADPHONE OUT DRIVERS | ||||||
| Output common mode | First option | 1.35 | V | |||
| Second option | 1.5 | |||||
| Third option | 1.65 | |||||
| Fourth option | 1.8 | |||||
| Output volume control maximum setting | 9 | dB | ||||
| Output volume control step size | 1 | dB | ||||
| DAC DIGITAL INTERPOLATION(5): FILTER fS = 48 ksps, 25°C | ||||||
| Pass band | 0 | 0.45 fS | Hz | |||
| Pass-band ripple | ±0.06 | dB | ||||
| Transition band | 0.45 fS | 0.55 fS | Hz | |||
| Stop band | 0.55 fS | 7.5 fS | Hz | |||
| Stop-band attenuation | 65 | dB | ||||
| Group delay | 21 / fS | s | ||||
| DIGITAL I/O, 25°C | ||||||
| VIL | Input low level | –0.3 | 0.3 × VIOVDD | V | ||
| VIH | Input high level(4) | VIOVDD > 1.6 V | 0.7 × VIOVDD | V | ||
| VIOVDD < 1.6 V | 1.1 | |||||
| VOL | Output low level | 0.1 × VIOVDD | V | |||
| VOH | Output high level | 0.8 × VIOVDD | V | |||
| POWER CONSUMPTION, DRVDD, AVDD_DAC = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V | ||||||
| IDRVDD + IAVDD_DAC | RESET held low | 0.1 | μA | |||
| IDVDD | 0.2 | |||||
| IDRVDD + IAVDD_DAC | Mono ADC record, fS = 8 ksps, I2S slave, AGC off, no signal |
2.1 | mA | |||
| IDVDD | 0.5 | |||||
| IDRVDD + IAVDD_DAC | Stereo ADC record, fS = 8 ksps, I2S slave, AGC off, no signal |
4.1 | mA | |||
| IDVDD | 0.6 | |||||
| IDRVDD + IAVDD_DAC | Stereo ADC record, fS = 48 ksps, I2S slave, AGC off, no signal |
4.3 | mA | |||
| IDVDD | 2.5 | |||||
| IDRVDD + IAVDD_DAC | Stereo DAC playback to line out, analog mixer bypassed, fS = 48 ksps, I2S slave |
3.5 | mA | |||
| IDVDD | 2.3 | |||||
| IDRVDD + IAVDD_DAC | Stereo DAC playback to line out, fS = 48 ksps, I2S slave, no signal | 4.9 | mA | |||
| IDVDD | 2.3 | |||||
| IDRVDD + IAVDD_DAC | Stereo DAC playback to stereo single-ended headphone, fS = 48 ksps, I2S slave, no signal |
6.7 | mA | |||
| IDVDD | 2.3 | |||||
| IDRVDD + IAVDD_DAC | Stereo line in to stereo line out, no signal | 3.1 | mA | |||
| IDVDD | 0 | |||||
| IDRVDD + IAVDD_DAC | Extra power when PLL enabled | 1.4 | mA | |||
| IDVDD | 0.9 | |||||
| IDRVDD + IAVDD_DAC | All blocks powered down, headset detection enabled | 28 | μA | |||
| IDVDD | 2 | |||||
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16-Ω single-ended load.
(4) When VIOVDD < 1.6 V, minimum VIH is 1.1 V.
(5) Not production tested. Specified by design.
8.6 Switching Characteristics I2S/LJF/RJF In Master Mode
All specifications at 25°C, DVDD = 1.8 V.| PARAMETER | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| td(WS) | ADWS/WCLK delay time | VIOVDD = 1.1 V | 50 | ns | |
| VIOVDD = 3.3 V | 15 | ||||
| td(DO-WS) | ADWS/WCLK to DOUT delay time | VIOVDD = 1.1 V | 50 | ns | |
| VIOVDD = 3.3 V | 20 | ||||
| td(DO-BCLK) | BCLK to DOUT delay time | VIOVDD = 1.1 V | 50 | ns | |
| VIOVDD = 3.3 V | 15 | ||||
| ts(DI) | DIN setup time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 6 | ||||
| th(DI) | DIN hold time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 6 | ||||
| tr | Rise time | VIOVDD = 1.1 V | 30 | ns | |
| VIOVDD = 3.3 V | 10 | ||||
| tf | Fall time | VIOVDD = 1.1 V | 30 | ns | |
| VIOVDD = 3.3 V | 10 | ||||
8.7 Switching Characteristics I2S/LJF/RJF In Slave Mode
All specifications at 25°C, DVDD = 1.8 V.| PARAMETER | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| tH(BCLK) | BCLK high period | VIOVDD = 1.1 V | 70 | ns | |
| VIOVDD = 3.3 V | 35 | ||||
| tL(BCLK) | BCLK low period | VIOVDD = 1.1 V | 70 | ns | |
| VIOVDD = 3.3 V | 35 | ||||
| ts(WS) | ADWS/WCLK setup time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 6 | ||||
| th(WS) | ADWS/WCLK hold time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 6 | ||||
| td(DO-WS) | ADWS/WCLK to DOUT delay time (for LJF Mode only) | VIOVDD = 1.1 V | 50 | ns | |
| VIOVDD = 3.3 V | 35 | ||||
| td(DO-BCLK) | BCLK to DOUT delay time | VIOVDD = 1.1 V | 50 | ns | |
| VIOVDD = 3.3 V | 20 | ||||
| ts(DI) | DIN setup time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 6 | ||||
| th(DI) | DIN hold time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 6 | ||||
| tr | Rise time | VIOVDD = 1.1 V | 8 | ns | |
| VIOVDD = 3.3 V | 4 | ||||
| tf | Fall time | VIOVDD = 1.1 V | 8 | ns | |
| VIOVDD = 3.3 V | 4 | ||||
8.8 Switching Characteristics DSP In Master Mode
All specifications at 25°C, DVDD = 1.8 V.| PARAMETER | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| td(WS) | ADWS/WCLK delay time | VIOVDD = 1.1 V | 50 | ns | |
| VIOVDD = 3.3 V | 15 | ||||
| td(DO-BCLK) | BCLK to DOUT delay time | VIOVDD = 1.1 V | 50 | ns | |
| VIOVDD = 3.3 V | 15 | ||||
| ts(DI) | DIN setup time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 6 | ||||
| th(DI) | DIN hold time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 6 | ||||
| tr | Rise time | VIOVDD = 1.1 V | 30 | ns | |
| VIOVDD = 3.3 V | 10 | ||||
| tf | Fall time | VIOVDD = 1.1 V | 30 | ns | |
| VIOVDD = 3.3 V | 10 | ||||
8.9 Switching Characteristics DSP In Slave Mode
All specifications at 25°C, DVDD = 1.8 V.| PARAMETER | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| tH(BCLK) | BCLK high period | VIOVDD = 1.1 V | 70 | ns | |
| VIOVDD = 3.3 V | 35 | ||||
| tL(BCLK) | BCLK low period | VIOVDD = 1.1 V | 70 | ns | |
| VIOVDD = 3.3 V | 35 | ||||
| ts(WS) | ADWS/WCLK setup time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 8 | ||||
| th(WS) | ADWS/WCLK hold time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 8 | ||||
| td(DO-BCLK) | BCLK to DOUT delay time | VIOVDD = 1.1 V | 50 | ns | |
| VIOVDD = 3.3 V | 20 | ||||
| ts(DI) | DIN setup time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 6 | ||||
| th(DI) | DIN hold time | VIOVDD = 1.1 V | 10 | ns | |
| VIOVDD = 3.3 V | 6 | ||||
| tr | Rise time | VIOVDD = 1.1 V | 8 | ns | |
| VIOVDD = 3.3 V | 4 | ||||
| tf | Fall time | VIOVDD = 1.1 V | 8 | ns | |
| VIOVDD = 3.3 V | 4 | ||||
Figure 1. I2S/LJF/RJF Timing In Master Mode
Figure 2. I2S/LJF/RJF Timing In Slave Mode
Figure 3. DSP Timing In Master Mode
Figure 4. DSP Timing In Slave Mode
8.10 Typical Characteristics
Figure 5. Total Harmonic Distortion vsHeadphone Out Power
Figure 7. MICBIAS Voltage vs Supply Voltage
Figure 9. Left DAC FFT
Figure 11. Left ADC FFT
Figure 6. Signal-To-Noise Ratio vs ADC PGA Setting
Figure 8. MICBIAS Voltage vs Free-Air Temperature
Figure 10. Right DAC FFT
Figure 12. Right ADC FFT