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ZHCSK12A July 2019 – October 2019 TLV320ADC6140

PRODUCTION DATA.

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

RTW|24

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

8.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing

Certain events in the device may require host processor intervention and can be used to trigger interrupts to the host processor. One such event is an audio serial interface (ASI) bus error. The device powers down the record channels if any faults are detected with the ASI bus error clocks, such as:

Invalid FSYNC frequency
Invalid SBCLK to FSYNC ratio
Long pauses of the SBCLK or FSYNC clocks

When an ASI bus clock error is detected, the device shuts down the record channel as quickly as possible. After all ASI bus clock errors are resolved, the device volume ramps back to its previous state to recover the record channel. During an ASI bus clock error, the internal interrupt request (IRQ) interrupt signal asserts low if the clock error interrupt mask register bit INT_MASK0[7], P0_R51_D7 is set low. The clock fault is also available for readback in the latched fault status register bit INT_LTCH0, P0_R54, which is a read-only register. Reading the latched fault status register, INT_LTCH0, clears all latched fault status. The device can be additionally configured to route the internal IRQ interrupt signal on the GPIO1 or GPOx pins and also can be configured as open-drain outputs so that these pins can be wire-ANDed to the open-drain interrupt outputs of other devices.

The IRQ interrupt signal can either be configured as active low or active high polarity by setting the INT_POL, P0_R50_D7 register bit. This signal can also be configured as a single pulse or a series of pulses by programming the INT_EVENT[1:0], P0_R50_D[6:5] register bits. If the interrupts are configured as a series of pulses, the events trigger the start of pulses that stop when the latched fault status register is read to determine the cause of the interrupt.

The device also supports read-only live-status registers to determine if the channels are powered up or down and if the device is in sleep mode or not. These status registers are located in P0_R118, DEV_STS0 and P0_R119, DEV_STS1.

The device has a multifunctional GPIO1 pin that can be configured for a desired specific function. Additionally, if the channel is not used for analog input recording, then the analog input pins for that channel (INxP and INxM) can be repurposed as multifunction pins (GPIx and GPOx) by configuring the CHx_INSRC[1:0] register bits located in the CHx_CFG0 register. The maximum number of GPO pins supported by the device is four and the maximum number of GPI pins are four. Table 48 shows all possible allocations of these multifunctional pins for the various features.

Table 48. Multifunction Pin Assignments

ROW	Pin Function⁽⁴⁾	GPIO1	GPO1	GPO2	GPO3	GPO4	GPI1	GPI2	GPI3	GPI4
—	—	GPIO1_CFG	GPO1_CFG	GPO2_CFG	GPO3_CFG	GPO4_CFG	GPI1_CFG	GPI2_CFG	GPI3_CFG	GPI4_CFG
—	—	P0_R33[7:4]	P0_R34[7:4]	P0_R35[7:4]	P0_R36[7:4]	P0_R37[7:4]	P0_R43[6:4]	P0_R43[2:0]	P0_R44[6:4]	P0_R44[2:0]
A	Pin disabled	S⁽¹⁾	S (default)	S (default)	S (default)	S (default)	S (default)	S (default)	S (default)	S (default)
B	General-purpose output (GPO)	S	S	S	S	S	NS⁽²⁾	NS	NS	NS
C	Interrupt output (IRQ)	S (default)	S	S	S	S	NS	NS	NS	NS
D	Secondary ASI output (SDOUT2)⁽³⁾	S	S	S	S	S	NS	NS	NS	NS
E	PDM clock output (PDMCLK)	S	S	S	S	S	NS	NS	NS	NS
F	MiCBIAS on/off input (BIASEN)	S	NS	NS	NS	NS	NS	NS	NS	NS
G	General-purpose input (GPI)	S	NS	NS	NS	NS	S	S	S	S
H	Master clock input (MCLK)	S	NS	NS	NS	NS	S	S	S	S
I	ASI daisy-chain input (SDIN)	S	NS	NS	NS	NS	S	S	S	S
J	PDM data input 1 (PDMDIN1)	S	NS	NS	NS	NS	S	S	S	S
K	PDM data input 2 (PDMDIN2)	S	NS	NS	NS	NS	S	S	S	S
L	PDM data input 3 (PDMDIN3)	S	NS	NS	NS	NS	S	S	S	S
M	PDM data input 4 (PDMDIN4)	S	NS	NS	NS	NS	S	S	S	S

(1) S means the feature mentioned in this row is supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.

(2) NS means the feature mentioned in this row is not supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.

(3) For the high-speed ASI output, GPIO1 must be used instead of GPOx for the secondary ASI output. GPOx can be used only if the bus speed requirement is less than 6.144 MHz.

(4) Only the GPIO1 pin is with reference to the IOVDD supply, the other GPOx and GPIx pins are with reference to the AVDD supply and their primary pin functions are for the PDMCLK or PDMDIN function.

Each GPOx or GPIOx pin can be independently set for the desired drive configurations setting using the GPOx_DRV[3:0] or GPIO1_DRV[3:0] register bits. Table 49 lists the drive configuration settings.

Table 49. GPIO or GPOx Pins Drive Configuration Settings

P0_R33_D[3:0] : GPIO1_DRV[3:0]	GPIO OUTPUT DRIVE CONFIGURATION SETTINGS FOR GPIO1
000	The GPIO1 pin is set to high impedance (floated)
001	The GPIO1 pin is set to be driven active low or active high
010 (default)	The GPIO1 pin is set to be driven active low or weak high (on-chip pullup)
011	The GPIO1 pin is set to be driven active low or Hi-Z (floated)
100	The GPIO1 pin is set to be driven weak low (on-chip pulldown) or active high
101	The GPIO1 pin is set to be driven Hi-Z (floated) or active high
110 and 111	Reserved (do not use these settings)

Similarly, the GPO1 to GPO4 pins can be configured using the GPO1_DRV(P0_R34) to GPO4_DRV(P0_R37) register bits, respectively.

When configured as a general-purpose output (GPO), the GPIO1 or GPOx pin values can be driven by writing the GPIO_VAL or GPOx_VAL, P0_R41 registers. The GPIO_MON, P0_R42 register can be used to readback the status of the GPIO1 pin when configured as a general-purpose input (GPI). Similarly, the GPI_MON, P0_R47 register can be used to readback the status of the GPIx pins when configured as a general-purpose input (GPI).