ZHCSK12A July 2019 – October 2019 TLV320ADC6140
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| f(PDMCLK) | PDMCLK clock frequency | 0.768 | 6.144 | MHz | ||
| tH(PDMCLK) | PDMCLK high pulse duration | 72 | ns | |||
| tL(PDMCLK) | PDMCLK low pulse duration | 72 | ns | |||
| tr(PDMCLK) | PDMCLK rise time | 10% - 90% rise time | 18 | ns | ||
| tf(PDMCLK) | PDMCLK fall time | 90% - 10% fall time | 18 | ns | ||
Figure 1. I2C Interface Timing Diagram
Figure 2. SPI Interface Timing Diagram
Figure 3. TDM (With BCLK_POL = 1), I2S, and LJ Interface Timing Diagram
Figure 4. PDM Digital Microphone Interface Timing Diagram