ZHCSMM8A December 2020 – June 2021 TLV320ADC3120
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| td(SDOUT-BCLK) | BCLK to SDOUT delay | 50% of BCLK to 50% of SDOUT | 3 | 18 | ns | |
| td(SDOUT-FSYNC) | FSYNC to SDOUT delay in TDM or LJ mode (for MSB data with TX_OFFSET = 0) | 50% of FSYNC to 50% of SDOUT | 18 | ns | ||
| f(BCLK) | BCLK output clock frequency: master mode (1) | 24.576 | MHz | |||
| tH(BCLK) | BCLK high pulse duration: master mode | 14 | ns | |||
| tL(BCLK) | BCLK low pulse duration: master mode | 14 | ns | |||
| td(FSYNC) | BCLK to FSYNC delay: master mode | 50% of BCLK to 50% of FSYNC | 3 | 18 | ns | |
| tr(BCLK) | BCLK rise time: master mode | 10% - 90% rise time | 8 | ns | ||
| tf(BCLK) | BCLK fall time: master mode | 90% - 10% fall time | 8 | ns | ||