ZHCSLG5C July 2020 – March 2022 TLIN2027-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| D112V | Duty Cycle 1 (ISO/DIS 17987 Param 27)(1) | THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 4 V to 7.4 V, tBIT = 50 μs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.396 | |||
| D112V | Duty Cycle 1 | THREC(MAX) = 0.625 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7.4 V to 9.4 V, tBIT = 50 μs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.368 | |||
| D112V | Duty Cycle 1 (ISO/DIS 17987 Param 27) | THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 9.4 V to 18 V, tBIT = 50 μs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.396 | |||
| D212V | Duty Cycle 2 (ISO/DIS 17987 Param 28) | THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 4 V to 7.4 V, tBIT = 50 μs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.581 | |||
| D212V | Duty Cycle 2 | THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 7.4 V to 9.4 V, tBIT = 50 μs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.67 | |||
| D212V | Duty Cycle 2 (ISO/DIS 17987 Param 28) | THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 9.4 V to 18 V, tBIT = 50 μs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.581 | |||
| D312V | Duty Cycle 3 (ISO/DIS 17987 Param 29) | THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 7 V to 18 V, tBIT = 96 μs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.417 | |||
| D312V | Duty Cycle 3 | THREC(MAX) = 0.645 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 4 V to 7 V, tBIT = 96 μs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.417 | |||
| D412V | Duty Cycle 4 (ISO/DIS 17987 Param 30) | THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 4.6 V to 7.4 V, tBIT = 96 μs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.59 | |||
| D412V | Duty Cycle 4 | THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 7.4 V to 9.4 V, tBIT = 96 μs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.6 | |||
| D412V | Duty Cycle 4 (ISO/DIS 17987 Param 30) | THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 7.4 V to 18 V, tBIT = 96 μs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.59 | |||
| D124V | Duty Cycle 1 (ISO/DIS 17987 Param 72)(1) | THREC(MAX) = 0.710 x VSUP, THDOM(MAX) = 0.544 x VSUP, VSUP = 15 V to 36 V, tBIT = 50 μs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.33 | |||
| D224V | Duty Cycle 2 (ISO/DIS 17987 Param 73) | THREC(MIN) = 0.446 x VSUP, THDOM(MIN) = 0.302 x VSUP, VSUP = 15.6 V to 36 V, tBIT = 50 μs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.642 | |||
| D324V | Duty Cycle 3 (ISO/DIS 17987 Param 74) | THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 36 V, tBIT = 96 μs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.386 | |||
| D324V | Duty Cycle | THREC(MAX) = 0.645 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT = 96 μs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.386 | |||
| D424V | Duty Cycle 4 (ISO/DIS 17987 Param 75) | THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 4.6 V to 36 V, tBIT = 96 μs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12) | 0.591 | |||