ZHCSLG5C July 2020 – March 2022 TLIN2027-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Power Supply | ||||||
| VSUP | Operational supply voltage (ISO/DIS 17987 Param 10, 53) | Device is operational beyond the LIN defined nominal supply voltage range.See Figure 8-1 and Figure 8-2 | 4 | 48 | V | |
| VSUP | Nominal supply voltage (ISO/DIS 17987 Param 10, 53) | Normal and Standby Modes: ramp VSUP while LIN signal is a 10 kHz square wave with 50 % duty cycle and 36V swing. See Figure 8-1 and Figure 8-2 | 4 | 48 | V | |
| Sleep Mode | 4 | 48 | V | |||
| UVSUP | Under voltage VSUP threshold | Min is falling edge and Max is rising edge | 2.9 | 3.85 | V | |
| UVHYS | Delta hysteresis voltage for VSUP under voltage threshold | 0.2 | V | |||
| ISUP | Supply current | Normal Mode: EN = high, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF (See Figure 8-7) | 5 | mA | ||
| Standby Mode: EN = low, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF (See Figure 8-7) | 1 | 2.1 | mA | |||
| ISUP | Supply current | Normal Mode: EN = high, bus recessive (LIN = VSUP) | 400 | 700 | μA | |
| Standby Mode: EN = low, bus recessive (LIN = VSUP) | 20 | 35 | μA | |||
| Sleep Mode: 4.0 V < VSUP ≤ 27 V, LIN = VSUP, EN = 0 V, TXD and RXD floating | 9 | 15 | μA | |||
| Sleep Mode: 27 V < VSUP ≤ 48 V, LIN = VSUP, EN = 0 V, TXD and RXD floating | 30 | μA | ||||
| TSD | Thermal shutdown | 165 | ℃ | |||
| TSD(HYS) | Thermal shutdown hysteresis | 15 | ℃ | |||
| RXD OUTPUT PIN (OPEN DRAIN) | ||||||
| VOL | Output low voltage | RPU = 2.4 k? | 0.6 | V | ||
| IOL | Low level output current, open drain | LIN = 0 V, RXD = 0.4 V | 1.5 | mA | ||
| IILG | Leakage current, high-level | LIN = VSUP, RXD = 5 V | –5 | 0 | 5 | μA |
| TXD INPUT PIN | ||||||
| VIL | Low level input voltage | –0.3 | 0.8 | V | ||
| VIH | High level input voltage | 2 | 5.5 | V | ||
| IILG | Low level input leakage current | TXD = low | –5 | 0 | 5 | μA |
| RTXD | Internal pull-down resistor value | 125 | 350 | 800 | kΩ | |
| LIN PIN | ||||||
| VOH | HIGH level output voltage | LIN recessive, TXD = high, IO = 0 mA, VSUP = 7 V to 48 V(1) | 0.85 | VSUP | ||
| LIN recessive, TXD = high, IO = 0 mA, VSUP = 4 V ≤ VSUP < 7 V(1) | 3 | V | ||||
| VOL | LOW level output voltage | LIN dominant, TXD = low, VSUP = 7 V to 48 V(1) | 0.2 | VSUP | ||
| LIN dominant, TXD = low, VSUP = 4 V ≤ VSUP < 7 V(1) | 1.2 | V | ||||
| VSUP_NON_OP | VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11, 54/56) | TXD & RXD open LIN = 4 V to 58 V | –0.3 | 58 | V | |
| IBUS_LIM | Limiting current (ISO/DIS 17987 Param 12) | TXD = 0 V, VLIN = 36 V, RMEAS = 440 Ω, VSUP = 36 V, VBUSdom < 4.518 V See Figure 8-6 | 40 | 90 | 200 | mA |
| IBUS_PAS_dom | Receiver leakage current, dominant (ISO/DIS 17987 Param 13, 58) | LIN = 0 V, VSUP = 24 V Driver off/recessive Figure 8-7 | –1 | mA | ||
| IBUS_PAS_rec1 | Receiver leakage current, recessive (ISO/DIS 17987 Param 14, 59) | LIN > VSUP, 4 V ≤ VSUP ≤ 45 V Driver off; Figure 8-8 | 20 | μA | ||
| IBUS_PAS_rec2 | Receiver leakage current, recessive (ISO/DIS 17987 Param 14, 59) | LIN = VSUP, Driver off; Figure 8-8 | –5 | 5 | μA | |
| IBUS_NO_GND | Leakage current, loss of ground (ISO/DIS 17987 Param 15, 60) | GND = VSUP, VSUP = 27 V, LIN = 0 V; Figure 8-9 | –1 | 1 | mA | |
| IBUS_NO_GND | Leakage current, loss of ground (ISO/DIS 17987 Param 15, 60) | GND = VSUP, VSUP ≥ 36 V, LIN = 0 V; Figure 8-9 | –1.5 | 1.5 | mA | |
| IBUS_NO_BAT | Leakage current, loss of supply (ISO/DIS 17987 Param 16, 61) | LIN = 48 V, VSUP = GND; Figure 8-10 | 5 | μA | ||
| VBUSdom | Low level input voltage (ISO/DIS 17987 Param 17, 62) | LIN dominant (including LIN dominant for wake up) See Figure 8-4, Figure 8-3 | 0.4 | VSUP | ||
| VBUSrec | High level input voltage (ISO/DIS 17987 Param 18, 63) | LIN recessive See Figure 8-4, Figure 8-3 | 0.6 | VSUP | ||
| VBUS_CNT | Receiver center threshold (ISO/DIS 17987 Param 19, 64) | VBUS_CNT = (VIL + VIH)/2 See Figure 8-4, Figure 8-3 | 0.475 | 0.5 | 0.525 | VSUP |
| VHYS | Hysteresis voltage (ISO/DIS 17987 Param 20, 65) | VHYS = (VIL - VIH) See Figure 8-4, Figure 8-3 | 0.175 | VSUP | ||
| VSERIAL_DIODE | Serial diode LIN term pull-up path | By design and characterization | 0.4 | 0.7 | 1 | V |
| RPU-LIN | Internal pull-up resistor to VSUP | Normal and standby modes | 20 | 45 | 60 | kΩ |
| IRSLEEP | Pull-up current source to VSUP | Sleep mode, VSUP = 27 V, LIN = GND | –2 | –20 | μA | |
| CLINPIN | Capacitance of the LIN pin | VSUP = 14 V | 25 | pF | ||
| EN INPUT PIN | ||||||
| VIL | Low level input voltage | –0.3 | 0.8 | V | ||
| VIH | High level input voltage | 2 | 5.5 | V | ||
| VIT | Hysteresis voltage | By design and characterization | 50 | 500 | mV | |
| IILG | Low level input current | EN = low | –5 | 0 | 5 | μA |
| REN | Internal pull-down resistor | 125 | 205 | 800 | kΩ | |