ZHCSI07D April 2018 – June 2022 TLIN1024-Q1
PRODUCTION DATA
Figure 7-1 Test System: Operating Voltage Range with RX and TX Access
Figure 7-2 RX Response: Operating Voltage Range
Figure 7-3 LIN Bus Input Signal
Figure 7-4 LIN Receiver Test with RX Access
Figure 7-5 VSUP_NON_OP
Figure 7-6 Test Circuit for IBUS_LIM at Dominant State (Driver on)
Figure 7-7 Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V
Figure 7-8 Test Circuit for IBUS_PAS_rec
Figure 7-9 Test Circuit for IBUS_NO_GND Loss of GND
Figure 7-10 Test Circuit for IBUS_NO_BAT Loss of Battery
Figure 7-11 Test Circuit Slope Control and Duty Cycle
Figure 7-12 Definition of Bus Timing Parameters
Figure 7-13 Propagation Delay Test Circuit
Figure 7-14 Propagation Delay
Figure 7-15 Mode Transitions
Figure 7-16 Wake Up Through EN
Figure 7-17 Wake Up Through LIN
Figure 7-18 Test Circuit for AC Characteristics