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SLIS142D December 2012 – September 2016 TLC6C598-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PW|16
- MPDS361B
D|16
- MPDS178G

散熱焊盤機械數據 (封裝 | 引腳)

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC	Logic supply voltage	–0.3	8	V
V_I	Logic input-voltage range	–0.3	8	V
V_DS	Power DMOS drain-to-source voltage	–0.3	42	V
	Continuous total dissipation	See Thermal Information
T_A	Operating ambient temperature	–40	125	°C
T_J	Operating junction temperature range	–40	150	°C
T_stg	Storage temperature range	–55	165	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾		±2000	V
		Charged device model (CDM), per AEC Q100-011	All pins	±750
		Charged device model (CDM), per AEC Q100-011	Corner pins (1, 8, 9, and 16)	±750

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

		MIN	MAX	UNIT
V_CC	Supply voltage	3	5.5	V
V_IH	High-level input voltage	2.4		V
V_IL	Low-level input voltage		0.7	V
T_A	Operating ambient temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TLC6C598-Q1		UNIT
		PW (TSSOP)	D (SOIC)
		16 PINS	16 PINS
R_θJA	Junction-to-ambient thermal resistance	129.4	100	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	55.4	45	°C/W
R_θJB	Junction-to-board thermal resistance	65.8	40	°C/W
ψ_JT	Junction-to-top characterization parameter	9.9	10	°C/W
ψ_JB	Junction-to-board characterization parameter	65.2	40	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	NA	NA	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

V_CC = 5 V, T_C = 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
	DRAIN0 to DRAIN7. Drain-to-source voltage					40	V
V_OH	High-level output voltage, SER OUT	I_OH = –20 μA	V_CC = 5 V	4.9	4.99		V
V_OH	High-level output voltage, SER OUT	I_OH = −4 mA	V_CC = 5 V	4.5	4.69		V
V_OL	Low-level output voltage, SER OUT	I_OH = 20 μA	V_CC = 5 V		0.001	0.01	V
V_OL	Low-level output voltage, SER OUT	I_OH = 4 mA	V_CC = 5 V		0.25	0.4	V
I_IH	High-level input current	V_CC = 5 V, V_I = V_CC			0.2		μA
I_IL	Low-level input current	V_CC = 5 V, V_I = 0			–0.2		μA
I_CC	Logic supply current	V_CC = 5 V, no clock signal	All outputs off		0.1	1	μA
I_CC	Logic supply current	V_CC = 5 V, no clock signal	All outputs on		88	160	μA
I_CC(FRQ)	Logic supply current at frequency	f_SRCK = 5 MHz, C_L = 30 pF	All outputs on		200		μA
I_DSX	Off-state drain current	V_DS = 30 V	V_CC = 5 V			0.1	μA
I_DSX	Off-state drain current	V_DS = 30 V, T_C = 125°C	V_CC = 5 V		0.15	0.3	μA
r_DS(on)	Static drain-source on-state resistance	I_D = 20 mA, V_CC = 5 V, T_A = 25°C, Single channel ON		6	7.41	8.6	Ω
		I_D = 20 mA, V_CC = 5 V, T_A = 25°C, All channels ON		6.7	8.3	9.6
		I_D = 20 mA, V_CC = 3.3 V, T_A = 25°C, Single channel ON		7.9	9.34	11.2
		I_D = 20 mA, V_CC = 3.3 V, T_A = 25°C, All channels ON		8.7	10.25	12.3
		I_D = 20 mA, V_CC = 5 V, T_A = 125°C, Single channel ON		9.1	11.13	12.9
		I_D = 20 mA, V_CC = 5 V, T_A = 125°C, All channels ON		10.3	12.28	14.5
		I_D = 20 mA, V_CC = 3.3 V, T_A = 125°C, Single channel ON		11.6	13.69	16.4
		I_D = 20 mA, V_CC = 3.3 V, T_A = 125°C, All channels ON		12.8	14.89	18.2
T_SHUTDOWN	Thermal shutdown trip point			150	175	200	ºC
T_hys	Hysteresis				15		ºC

6.6 Timing Requirements

		MIN	UNIT
t_su	Setup time, SER IN high before SRCK↑	15	ns
t_h	Hold time, SER IN high after SRCK↑	15	ns
t_w	SER IN pulse duration	40	ns

6.7 Switching Characteristics

V_CC = 5 V, T_J = 25°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH	Propagation delay time, low-to-high-level output from G	C_L = 30 pF, I_D= 48 mA		220		ns
t_PHL	Propagation delay time, high-to-low-level output from G			75		ns
t_r	Rise time, drain output			210		ns
t_f	Fall time, drain output			128		ns
t_pd	Propagation delay time, SRCK↓ to SER OUT	C_L = 30 pF, I_D = 48 mA		49.4		ns
t_or	SER OUT rise time (10% to 90%)	C_L = 30 pF		20		ns
t_of	SER OUT fall time (90% to 10%)	C_L = 30 pF		20		ns
f_(SRCK)	Serial clock frequency	C_L = 30 pF, I_D = 20 mA			10	MHz
t_{SRCK_WH}	SRCK pulse duration, high		30			ns
t_{SRCK_WL}	SRCK pulse duration, low		30			ns

6.8 Timing Waveforms

Figure 1 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift register clock (SRCK) because there is a phase inverter at SER OUT (see Figure 13). As a result, it takes seven and a half periods of SRCK for data to transfer from SER IN to SER OUT.