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ZHCSEQ9A March 2016 – March 2016 TLC59116-Q1

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

PW|28
- MPDS364

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

zhcseq9a_oa

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage	0	7	V
V_I	Input voltage	–0.4	V_CC + 0.4	V
V_O	Output voltage	–0.5	20	V
I_O	Output current per channel		120	mA
T_J	Junction temperature	–40	150	°C
T_stg	Storage temperature	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±1500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

All unused inputs of the device must be held at V_CC or GND to ensure proper device operation

				MIN	MAX	UNIT
V_CC	Supply voltage			3	5.5	V
V_IH	High-level input voltage	SCL, SDA, RESET, A0, A1, A2, A3		0.7 × V_CC	V_CC	V
V_IL	Low-level input voltage	SCL, SDA, RESET, A0, A1, A2, A3		0	0.3 × V_CC	V
V_O	Supply voltage to output pins	OUT0 to OUT15			17	V
I_OL	Low-level output current sink	SDA	V_CC = 3 V		20	mA
I_OL	Low-level output current sink	SDA	V_CC = 5 V		30	mA
I_O	Output current per channel	OUT0 to OUT15		5	120	mA
T_A	Operating free-air temperature			–40	105	°C

7.4 Thermal Information

THERMAL METRIC ⁽¹⁾		TLC59116-Q1	UNIT
		PW (TSSOP)
		28 PINS
R_θJA	Junction-to-ambient thermal resistance	78	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	18.8	°C/W
R_θJB	Junction-to-board thermal resistance	36	°C/W
ψ_JT	Junction-to-top characterization parameter	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	35.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

V_CC = 3 V to 5.5 V, T_A = –40°C to +105°C (unless otherwise noted)

PARAMETER			TEST CONDITIONS		MIN	TYP ⁽¹⁾	MAX	UNIT
I_I	Input / output leakage current	SCL, SDA, A0, A1, A2, A3, RESET	V_I = V_CC or GND				±0.3	μA
	Output leakage current	OUT0 to OUT15	V_O = 17 V, T_J = 25°C				0.5	μA
V_POR	Power-on reset voltage					2.5		V
I_OL	Low-level output current	SDA	V_CC = 3 V, V_OL = 0.4 V		20			mA
I_OL	Low-level output current	SDA	V_CC = 5 V, V_OL = 0.4 V		30			mA
I_O(1)	Output current 1	OUT0 to OUT15	V_O = 0.6 V, R_ext= 720 Ω, CG = 0.992 ⁽³⁾			26		mA
	Output current error	OUT0 to OUT15	I_O = 26 mA, V_O = 0.6 V, R_ext = 720 Ω, T_J = 25°C				±10%
	Output channel to channel current error	OUT0 to OUT15	I_O = 26 mA, V_O = 0.6 V, R_ext = 720 Ω, T_J = 25°C				±6%
I_O(2)	Output current 2	OUT0 to OUT15	V_O = 0.8 V, R_ext = 360 Ω, CG = 0.992 ⁽³⁾			52		mA
	Output current error	OUT0 to OUT15	I_O = 52 mA, V_O = 0.8 V, R_ext = 360 Ω, T_J = 25°C				±8%
	Output channel to channel current error	OUT0 to OUT15	I_O = 52 mA, V_O = 0.8 V, R_ext = 360 Ω, T_J = 25°C				±6%
I_OUT vs V_OUT	Output current vs output voltage regulation	OUT0 to OUT15	V_O = 1 V to 3 V, I_O = 26 mA			±0.1		%/V
I_OUT vs V_OUT	Output current vs output voltage regulation	OUT0 to OUT15	V_O = 3 V to 5.5 V, I_O = 26 mA to 120 mA			±1		%/V
I_OUT,Th1	Threshold current 1 for error detection	OUT0 to OUT15	I_OUT,target = 26 mA			0.5 × I_TARGET%
I_OUT,Th2	Threshold current 2 for error detection	OUT0 to OUT15	I_OUT,target = 52 mA			0.5 × I_TARGET%
I_OUT,Th3	Threshold current 3 for error detection	OUT0 to OUT15	I_OUT,target = 104 mA			0.5 × I_TARGET%
T_SD	Overtemperature shutdown ⁽²⁾				150	175	200	°C
T_HYS	Restart hysteresis					15		°C
C_i	Input capacitance	SCL, A0, A1, A2, A3, RESET	V_I = V_CC or GND			5		pF
C_io	Input / output capacitance	SDA	V_I = V_CC or GND			8		pF
I_CC	Supply current		V_CC = 5.5 V	OUT0 to OUT15 = OFF, R_ext = Open			25	mA
				OUT0 to OUT15 = OFF, R_ext = 720 Ω			29
				OUT0 to OUT15 = OFF, R_ext = 360 Ω			32
				OUT0 to OUT15 = OFF, R_ext = 180 Ω			37
				OUT0 to OUT15 = ON, R_ext = 720 Ω			29
				OUT0 to OUT15 = ON, R_ext = 360 Ω			32
				OUT0 to OUT15 = ON, R_ext = 180 Ω			37

(1) All typical values are at T_A = 25°C.

(2) Specified by design

(3) CG is the Current Gain and is defined in Table 13.

7.6 Timing Requirements

T_A = –40°C to +105°C

		I²C BUS	MIN	MAX	UNIT
I²C INTERFACE
f_SCL	SCL clock frequency ⁽¹⁾	STANDARD MODE	0	100	kHz
		FAST MODE	0	400
		FAST MODE PLUS	0	1000
t_BUF	I²C Bus free time between Stop and Start conditions	STANDARD MODE	4.7		μs
		FAST MODE	1.3
		FAST MODE PLUS	0.5
t_HD;STA	Hold time (repeated) Start condition	STANDARD MODE	4		μs
		FAST MODE	0.6
		FAST MODE PLUS	0.26
t_SU;STA	Set-up time for a repeated Start condition	STANDARD MODE	4.7		μs
		FAST MODE	0.6
		FAST MODE PLUS	0.26
t_SU;STO	Set-up time for Stop condition	STANDARD MODE	4		μs
		FAST MODE	0.6
		FAST MODE PLUS	0.26
t_HD;DAT	Data hold time	STANDARD MODE	0		ns
		FAST MODE	0
		FAST MODE PLUS	0
t_VD;ACK	Data valid acknowledge time ⁽²⁾	STANDARD MODE	0.3	3.45	μs
		FAST MODE	0.1	0.9
		FAST MODE PLUS	0.05	0.45
t_VD;DAT	Data valid time ⁽³⁾	STANDARD MODE	0.3	3.45	μs
		FAST MODE	0.1	0.9
		FAST MODE PLUS	0.05	0.45
t_SU;DAT	Data set-up time	STANDARD MODE	250		ns
		FAST MODE	100
		FAST MODE PLUS	50
t_LOW	Low period of SCL clock	STANDARD MODE	4.7		μs
		FAST MODE	1.3
		FAST MODE PLUS	0.5
t_HIGH	High period of SCL clock	STANDARD MODE	4		μs
		FAST MODE	0.6
		FAST MODE PLUS	0.26
t_f	Fall time of both SDA and SCL signals ⁽⁵⁾ ⁽⁶⁾	STANDARD MODE		300	ns
		FAST MODE	20+0.1C_b ⁽⁴⁾	300
		FAST MODE PLUS		120
t_r	Rise time of both SDA and SCL signals	STANDARD MODE		1000	ns
		FAST MODE	20+0.1C_b ⁽⁴⁾	300
		FAST MODE PLUS		120
t_SP	Pulse width of spikes that must be suppressed by the input filter ⁽⁷⁾	STANDARD MODE		50	ns
		FAST MODE		50
		FAST MODE PLUS		50
RESET
t_W	Reset pulse width	STANDARD MODE	10		ns
		FAST MODE	10
		FAST MODE PLUS	10
t_REC	Reset recovery time	STANDARD MODE	0		ns
		FAST MODE	0
		FAST MODE PLUS	0
t_RESET	Time to reset ⁽⁸⁾ ⁽⁹⁾	STANDARD MODE	400		ns
		FAST MODE	400
		FAST MODE PLUS	400

(1) The TLC59116-Q1 does not have a self timeout on the I²C Bus. The Master can issue a reset if needed.

(2) t_VD;ACK = time for ACK signal from SCL low to SDA (out) low.

(3) t_VD;DAT = minimum time for SDA data out to be valid following SCL low.

(4) C_b = Total capacitance of one bus line in pF

(5) A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_IL of the SCL signal) in order to bridge the undefined region of the SCL falling edge.

(6) The maximum t_f for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t_f) for the SDA output stage is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t_f.

(7) Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

(8) Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions.

(9) Upon reset, the full delay will be the sum of t_RESET and the RC time constant of the SDA bus.

7.7 Typical Characteristics

Figure 1. I_OUT,target vs R_ext

V_CC = 5 V	CG = 0.992	R_EXT = 720 Ω

Figure 3. Output Current vs Output Voltage across Temp

V_CC = 5 V	CG = 0.992

Figure 2. Output Current vs Output Voltage across Output Current

R_EXT = 720 Ω	All Channels ON

Figure 4. I_CC vs V_CC across Temp