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SLDS156B March 2009 – July 2015 TLC59108

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PW|20
- MPDS362A
RGY|20
- MPQF116H

散熱焊盤機械數據 (封裝 | 引腳)

RGY|20
- QFND041R

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage	0	7	V
V_I	Input voltage	–0.4	7	V
V_O	Output voltage	–0.5	20	V
I_O	Output current		120	mA
T_J	Junction temperature	–40	150	°C
T_stg	Storage temperature	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

⁽¹⁾				MIN	MAX	UNIT
V_CC	Supply voltage			3	5.5	V
V_IH	High-level input voltage	SCL, SDA, RESET, A0, A1, A2, A3		0.7 × V_CC	V_CC	V
V_IL	Low-level input voltage	SCL, SDA, RESET, A0, A1, A2, A3		0	0.3 × V_CC	V
V_O	Supply voltage to output pins	OUT0 to OUT7			17	V
I_OL	Low-level output current sink	SDA	V_CC = 3 V		20	mA
I_OL	Low-level output current sink	SDA	V_CC = 3 V		30	mA
I_O	Output current	OUT0 to OUT7		5	120	mA
T_A	Operating free-air temperature			–40	85	°C

(1) All unused inputs of the device must be held at V_CC or GND to ensure proper device operation.

7.4 Thermal Information

THERMAL METRIC ⁽¹⁾		TLC59108		UNIT
		PW (TSSOP)	RGY (VQFN)
		20 PINS	20 PINS
R_θJA	Junction-to-ambient thermal resistance	98.9	39.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	32.9	44.7	°C/W
R_θJB	Junction-to-board thermal resistance	49.9	14.8	°C/W
ψ_JT	Junction-to-top characterization parameter	1.7	1.0	°C/W
ψ_JB	Junction-to-board characterization parameter	49.3	14.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	–	7.6	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

V_CC = 3 V to 5.5 V, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER			TEST CONDITIONS		MIN	TYP ⁽¹⁾	MAX	UNIT
I_I	Input/output leakage current	SCL, SDA, A0, A1, A2, A3, RESET	V_I = V_CC or GND				±0.3	μA
	Output leakage current	OUT0 to OUT7	V_O = 17 V, T_J = 25°C				0.5	μA
V_POR	Power-on reset voltage					2.5		V
I_OL	Low-level output current	SDA	V_CC = 3 V, V_OL = 0.4 V		20			mA
I_OL	Low-level output current	SDA	V_CC = 5 V, V_OL = 0.4 V		30			mA
I_O(1)	Output current 1	OUT0 to OUT7	V_O = 0.6 V, R_ext= 720 Ω, CG = 0.992			26		mA
	Output current error	OUT0 to OUT7	I_O = 26 mA, V_O = 0.6 V, R_ext = 720 Ω, T_J = 25°C				±8%
	Output channel to channel current error	OUT0 to OUT7	I_O = 26 mA, V_O = 0.6 V, R_ext = 720 Ω, T_J = 25°C				±3%
I_O(2)	Output current 2	OUT0 to OUT7	VO = 0.8 V, R_ext = 360 Ω, CG = 0.992			52		mA
	Output current error	OUT0 to OUT7	I_O = 52 mA, V_O = 0.8 V, R_ext = 360 Ω, T_J = 25°C				±8%
	Output channel to channel current error	OUT0 to OUT7	I_O = 52 mA, V_O = 0.8 V, R_ext = 360 Ω, T_J = 25°C				±3%
I_OUT vs V_OUT	Output current vs output voltage regulation	OUT0 to OUT7	V_O = 1 V to 3 V, I_O = 26 mA			±0.1		%/V
I_OUT vs V_OUT	Output current vs output voltage regulation	OUT0 to OUT7	V_O = 3 V to 5.5 V, I_O = 26 mA to 120 mA			±1		%/V
I_OUT,Th1	Threshold current 1 for error detection	OUT0 to OUT7	I_OUT,target = 26 mA			0.5% × I_TARGET
I_OUT,Th2	Threshold current 2 for error detection	OUT0 to OUT7	I_OUT,target = 52 mA			0.5% × I_TARGET
I_OUT,Th3	Threshold current 3 for error detection	OUT0 to OUT7	I_OUT,target = 104 mA			0.5% × I_TARGET
T_SD	Overtemperature shutdown ⁽²⁾				150	175	200	°C
T_HYS	Restart hysteresis					15		°C
C_i	Input capacitance	SCL, A0, A1, A2, A3, RESET	V_I = V_CC or GND				5	pF
C_io	Input/output capacitance	SDA	V_I = V_CC or GND				5	pF
I_CC	Supply current		V_CC = 5.5 V	OUT0 to OUT7 = OFF, R_ext = Open			17	mA
				OUT0 to OUT7 = OFF, R_ext = 720 Ω			20
				OUT0 to OUT7 = OFF, R_ext = 360 Ω			23
				OUT0 to OUT7 = OFF, R_ext = 180 Ω			28
				OUT0 to OUT7 = ON, R_ext = 720 Ω			21
				OUT0 to OUT7 = ON, R_ext = 360 Ω			23
				OUT0 to OUT7 = ON, R_ext = 180 Ω			28

(1) All typical values are at T_A = 25°C.

(2) Specified by design

7.6 Timing Requirements

T_A = –40°C to 85°C

		STANDARD MODE I²C BUS		FAST MODE I²C BUS		FAST MODE PLUS I²C BUS		UNIT
		MIN	MAX	MIN	MAX	MIN	MAX	UNIT
I²C Interface
f_SCL	SCL clock frequency	0	100	0	400	0	1000	kHz
t_BUF	I²C bus free time between stop and start	4.7		1.3		0.5		μs
t_HD;STA	Hold time (repeated) Start condition	4		0.6		0.26		μs
t_SU;STA	Set-up time for a repeated Start condition	4.7		0.6		0.26		μs
t_SU;STO	Set-up time for Stop condition	4		0.6		0.26		μs
t_HD;DAT	Data hold time	0		0		0		ns
t_VD;ACK	Data valid acknowledge time ⁽¹⁾	0.3	3.45	0.1	0.9	0.05	0.45	μs
t_VD;DAT	Data valid time ⁽²⁾	0.3	3.45	0.1	0.9	0.05	0.45	μs
t_SU;DAT	Data set-up time	250		100		50		ns
t_LOW	Low period of the SCL clock	4.7		1.3		0.5		μs
t_HIGH	High period of the SCL clock	4		0.6		0.26		μs
t_f	Fall time of both SDA and SCL signals ⁽⁴⁾⁽⁵⁾		300	20+0.1C_b⁽³⁾	300		120	ns
t_r	Rise time of both SDA and SCL signals		1000	20+0.1C_b⁽³⁾	300		120	ns
t_SP	Pulse width of spikes that must be suppressed by the input filter ⁽⁶⁾		50		50		50	ns
Reset
t_W	Reset pulse width	10		10		10		ns
t_REC	Reset recovery time	0		0		0		ns
t_RESET	Time to reset ⁽⁷⁾⁽⁸⁾	400		400		400		ns

(1) t_VD;ACK = time for Acknowledgment signal from SCL low to SDA (out) low.

(2) t_VD;DAT = minimum time for SDA data out to be valid following SCL low.

(3) C_b = total capacitance of one bus line in pF.

(4) A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_IL of the SCL signal) in order to bridge the undefined region of the SCL falling edge.

(5) The maximum t_f for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t_f) for the SDA output stage is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t_f.

(6) Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns

(7) Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions.

(8) Upon reset, the full delay is the sum of t_RESET and the RC time constant of the SDA bus.

7.7 Typical Characteristics

Figure 1. LED Current vs R_EXT Resistance

Figure 2. Output Current vs Output Voltage