ZHCSH32 November 2017 TLA2021 , TLA2022 , TLA2024
PRODUCTION DATA.
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| STANDARD-MODE | |||||
| fSCL | SCL clock frequency | 10 | 100 | kHz | |
| tLOW | Pulse duration, SCL low | 4.7 | µs | ||
| tHIGH | Pulse duration, SCL high | 4.0 | µs | ||
| tHD;STA | Hold time, (repeated) START condition.
After this period, the first clock pulse is generated. |
4 | µs | ||
| tSU;STA | Setup time, repeated START condition | 4.7 | µs | ||
| tHD;DAT | Hold time, data | 0 | µs | ||
| tSU;DAT | Setup time, data | 250 | ns | ||
| tr | Rise time, SCL, SDA | 1000 | ns | ||
| tf | Fall time, SCL, SDA | 250 | ns | ||
| tSU;STO | Setup time, STOP condition | 4.0 | µs | ||
| tBUF | Bus free time, between STOP and START condition | 4.7 | µs | ||
| tVD;DAT | Valid time, data | 3.45 | µs | ||
| tVD;ACK | Valid time, acknowledge | 3.45 | µs | ||
| FAST-MODE | |||||
| fSCL | SCL clock frequency | 10 | 400 | kHz | |
| tLOW | Pulse duration, SCL low | 1.3 | µs | ||
| tHIGH | Pulse duration, SCL high | 0.6 | µs | ||
| tHD;STA | Hold time, (repeated) START condition.
After this period, the first clock pulse is generated. |
0.6 | µs | ||
| tSU;STA | Setup time, repeated START condition | 0.6 | µs | ||
| tHD;DAT | Hold time, data | 0 | µs | ||
| tSU;DAT | Setup time, data | 100 | ns | ||
| tr | Rise time, SCL, SDA | 20 | 300 | ns | |
| tf | Fall time, SCL, SDA | 300 | ns | ||
| tSU;STO | Setup time, STOP condition | 0.6 | µs | ||
| tBUF | Bus free time, between STOP and START condition | 1.3 | µs | ||
| tVD;DAT | Valid time, data | 0.9 | µs | ||
| tVD;ACK | Valid time, acknowledge | 0.9 | µs | ||
Figure 1. I2C Timing Requirements