ZHCSKJ6 December 2019 TL16C750E
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagrams
- 9.3
Feature Description
- 9.3.1 UART Modes
- 9.3.2 Trigger Levels
- 9.3.3 Hardware Flow Control
- 9.3.4 Auto-RTS
- 9.3.5 Auto-CTS
- 9.3.6 Software Flow Control
- 9.3.7 Software Flow Control Example
- 9.3.8 Reset
- 9.3.9 Interrupts
- 9.3.10 Interrupt Mode Operation
- 9.3.11 Polled Mode Operation
- 9.3.12 Break and Timeout Conditions
- 9.3.13 Programmable Baud Rate Generator with Fractional Divisor
- 9.3.14 Fractional Divisor
- 9.4 Device Functional Modes
- 9.5
Register Maps
- 9.5.1 Registers Operations
- 9.5.2 Receiver Holding Register (RHR)
- 9.5.3 Transmit Holding Register (THR)
- 9.5.4 FIFO Control Register (FCR)
- 9.5.5 Line Control Register (LCR)
- 9.5.6 Line Status Register (LSR)
- 9.5.7 Modem Control Register (MCR)
- 9.5.8 Modem Status Register (MSR)
- 9.5.9 Interrupt Enable Register (IER)
- 9.5.10 Interrupt Identification Register (IIR)
- 9.5.11 Enhanced Feature Register (EFR)
- 9.5.12 Divisor Latches (DLL, DLH, DLF)
- 9.5.13 Transmission Control Register (TCR)
- 9.5.14 Trigger Level Register (TLR)
- 9.5.15 FIFO Ready Register
- 9.5.16 Alternate Function Register (AFR)
- 9.5.17 RS-485 Mode
- 9.5.18 IrDA Overview
- 9.5.19 IrDA Encoder Function
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PFB|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
9.3.4 Auto-RTS
Auto-RTS data flow control originates in the receiver block (see Figure 18). Figure 20 shows RTS functional timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the HALT trigger level in TCR[3:0]. When the receiver FIFO HALT trigger level is reached, RTS is deasserted. The sending device (for example, another UART) may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the deassertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO reaches the RESUME trigger level programmed via TCR[7:4]. This reassertion allows the sending device to resume transmission.
