When the driver enable pin, DE, is logic high (H), the differential outputs A/Y and B/Z follow the logic states at data input D. A logic high at D causes A/Y to turn high and B/Z to turn low. In this case, the differential output voltage defined as V_OD = V_A – V_B is positive. When D is low (L), the output states reverse: B/Z turns high, A/Y becomes low, and V_OD is negative.

When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant (X). The DE pin has an internal pull-down resistor to ground; thus, when left open the driver is disabled (Z = high-impedance) by default. The D pin has an internal pull-up resistor to V_IO; thus, when left open while the driver is enabled, output A/Y turns high and B/Z turns low.

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as V_ID = V_A – V_B is higher than the positive input threshold, V_TH+, the receiver output, R, turns high. When V_ID is lower than the negative input threshold, V_TH-, the receiver output, R, turns low. If V_ID is between V_TH+ and V_TH- the output is indeterminate.

When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of V_ID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).

Table 7-3 shows SLR (slew rate select) pin functionality. SLR has intergated pull-down, so the device remains in higher speed mode until SLR is pulled high which limits the slew rate and puts the device in slower speed mode.

Table shows the device behavior in undervoltage scenarios: