ZHCSJZ2F August 2019 – December 2024 THS6222
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| AC PERFORMANCE | |||||||
| SSBW | Small-signal bandwidth | AV = 5 V/V, RF = 1.5 kΩ, VO = 2 VPP | 250 | MHz | |||
| AV = 10 V/V, RF = 1.24 kΩ, VO = 2 VPP | 180 | ||||||
| AV = 15 V/V, RF = 1 kΩ, VO = 2 VPP | 165 | ||||||
| 0.1-dB bandwidth flatness | 17 | MHz | |||||
| LSBW | Large-signal bandwidth | VO = 16 VPP | 195 | MHz | |||
| SR | Slew rate (20% to 80%) | VO = 16-V step | 5500 | V/μs | |||
| Rise and fall time (10% to 90%) | VO = 2 VPP | 2.1 | ns | ||||
| HD2 | 2nd-order harmonic distortion | AV = 10 V/V, VO = 2 VPP, RL = 50 Ω |
Full bias, f = 1 MHz | –80 | dBc | ||
| Mid bias, f = 1 MHz | –78 | ||||||
| Low bias, f = 1 MHz | –78 | ||||||
| Full bias, f = 10 MHz | –61 | ||||||
| Mid bias, f = 10 MHz | –61 | ||||||
| Low bias, f = 10 MHz | –61 | ||||||
| HD3 | 3rd-order harmonic distortion | AV = 10 V/V, VO = 2 VPP, RL = 50 Ω |
Full bias, f = 1 MHz | –90 | dBc | ||
| Mid bias, f = 1 MHz | –86 | ||||||
| Low bias, f = 1 MHz | –83 | ||||||
| Full bias, f = 10 MHz | –69 | ||||||
| Mid bias, f = 10 MHz | –65 | ||||||
| Low bias, f = 10 MHz | –62 | ||||||
| en | Differential input voltage noise | f ≥ 1 MHz, input-referred, with and without 100 nF noise-decoupling capacitor on VCM pin | 2.5 | nV/√Hz | |||
| in+ | Noninverting input current noise | f ≥ 1 MHz, each amplifier | 1.4 | pA/√Hz | |||
| in- | Inverting input current noise | f ≥ 1 MHz, each amplifier | 18 | pA/√Hz | |||
| DC PERFORMANCE | |||||||
| ZOL | Open-loop transimpedance gain | 1300 | kΩ | ||||
| Input offset voltage (each amplifier) | ±12 | mV | |||||
| TA = –40°C | ±16 | ||||||
| TA = 85°C | ±11 | ||||||
| Noninverting input bias current | ±1 | μA | |||||
| TA = –40°C | ±1 | ||||||
| TA = 85°C | ±1 | ||||||
| Inverting input bias current | ±8 | μA | |||||
| TA = –40°C | ±7 | ||||||
| TA = 85°C | ±4 | ||||||
| INPUT CHARACTERISTICS | |||||||
| Common-mode input voltage | Each input with respect to midsupply | ±3.0 | V | ||||
| CMRR | Common-mode rejection ratio | Each input | 64 | dB | |||
| TA = –40°C | 67 | ||||||
| TA = 85°C | 62 | ||||||
| Noninverting differential input resistance | 10 || 2 | kΩ || pF | |||||
| Inverting input resistance | 43 | Ω | |||||
| COMMON-MODE BUFFER CHARACTERISTICS | |||||||
| VCM-OS | Common-mode offset voltage | Voltage at VCM with respect to midsupply | ±2.5 | mV | |||
| TA = –40°C | ±5 | ||||||
| TA = 85°C | ±1 | ||||||
| Common-mode voltage noise | With and without 100-nF VCM noise-decoupling capacitor, f ≥ 50 kHz | 20 | nV/√Hz | ||||
| Common-mode output resistance | f = DC | AC-coupled inputs | 650 | Ω | |||
| DC-coupled inputs | 520 | Ω | |||||
| OUTPUT CHARACTERISTICS | |||||||
| VO | Output voltage swing | RL = 100 Ω, RS = 0 Ω | ±9.7 | V | |||
| RL = 50 Ω, RS = 0 Ω | ±9.3 | ||||||
| RL = 25 Ω, RS = 0 Ω | ±8.4 | ||||||
| IO | Output current (sourcing and sinking) | RL = 25 Ω, RS = 0 Ω, based on VO specification | ±338 | mA | |||
| Short-circuit output current | ±0.81 | A | |||||
| ZO | Closed-loop output impedance | f = 1 MHz, differential | 0.03 | Ω | |||
| POWER SUPPLY | |||||||
| DGND | DGND pin voltage | VS– | 0 | VS+ – 5 | V | ||
| IS+ | Quiescent current | Full bias (BIAS-1 = 0, BIAS-2 = 0) | 19.5 | mA | |||
| Mid bias (BIAS-1 = 1, BIAS-2 = 0) | 15 | ||||||
| Low bias (BIAS-1 = 0, BIAS-2 = 1) | 10.4 | ||||||
| Bias off (BIAS-1 = 1, BIAS-2 = 1) | 1.1 | ||||||
| IS– | Quiescent current | Full bias (BIAS-1 = 0, BIAS-2 = 0) | 18.8 | mA | |||
| Mid bias (BIAS-1 = 1, BIAS-2 = 0) | 14.4 | ||||||
| Low bias (BIAS-1 = 0, BIAS-2 = 1) | 9.8 | ||||||
| Bias off (BIAS-1 = 1, BIAS-2 = 1) | 0.4 | ||||||
| Current through DGND pin | Full bias (BIAS-1 = 0, BIAS-2 = 0) | 0.8 | mA | ||||
| +PSRR | Positive power-supply rejection ratio | Differential | 83 | dB | |||
| –PSRR | Negative power-supply rejection ratio | Differential | 83 | dB | |||
| BIAS CONTROL | |||||||
| Bias control pin voltage | With respect to DGND, TA = –40°C to +85°C |
0 | 3.3 | 12 | V | ||
| Bias control pin logic threshold | Logic 1, with respect to DGND, TA = –40°C to +85°C |
2.1 | V | ||||
| Logic 0, with respect to DGND, TA = –40°C to +85°C |
0.8 | ||||||
| Bias control pin current(1) | BIAS-1, BIAS-2 = 0.5 V (logic 0) | –9.6 | μA | ||||
| BIAS-1, BIAS-2 = 3.3 V (logic 1) | 0.3 | 1 | |||||
| Open-loop output impedance | Off bias (BIAS-1 = 1, BIAS-2 = 1) | 70 || 5 | MΩ || pF | ||||