The THS4551 offers a trimmed input offset voltage and extremely low offset drift over the full –40°C to +125°C operating range. This offset voltage combines with several other error contribution terms to produce an initial 25°C output offset error band and then a drift over temperature. For each error term, a gain must be assigned to that term. For this analysis, only dc-coupled signal paths are considered. One new source of output error (versus the typical op amp analysis) arises from the effect mismatched resistor values and ratios can have on the two sides of the FDA. Any common-mode error or drift creates a differential output error through the slight mismatches arising from the external feedback and gain setting resistor tolerances or standard value constraints.

The error terms (25°C and drift), along with the gain to the output differential voltage, include input offset voltage and input offset current. Input offset voltage has a gain equal to the noise gain or 1 + R_F / R_G, where R_G is the total dc impedance from the input pins back to the source or a dc reference (typically ground). Input offset current has a gain to the differential output through the average feedback resistor value.

The remaining terms arise from an assumed range on both the absolute feedback resistor mismatch and the mismatch in the divider ratio on each side of the FDA. The first of these resistor mismatch terms is the input bias current that creates a differential output offset via R_F mismatch. For simplicity, the upper R_F and R_G values are termed R_F1 and R_G1 with a ratio of R_F1 / R_G1 ≡ G1. The lower elements are defined as R_F2 and R_G2 with a ratio of R_F2 / R_G2 ≡ G2. To compute worst-case contributions, a maximum variation in the design resistor tolerance is used in the absolute and ratio mismatches.

For instance, ±1% tolerance resistors are assumed, giving a worst-case G1 that is 2% higher than nominal and a G2 that is 2% lower than nominal with a worst-case R_F value mismatch of 2% as well. Using a 0.1% precision resistor reduces the gain for the input bias current, but because these precision resistors are usually only available in 1% value steps, a gain mismatch term may still need to be considered. For matched impedance designs with R_T and R_G1 on a single-ended to differential stage, the standard value constraint imposes a fixed mismatch in the initial feedback ratios with the tolerance of the resistors around the ratio if the non-signal input side uses a single resistor for R_G2.

Define the selected external resistor tolerance as ±T (so for 1% tolerance resistors, T = 0.01). Input bias current times the feedback resistor mismatch gain is ±2 × T × R_Fnom.

Anything that generates an output common-mode level or shift over temperature also generates an output differential error term if the two feedback ratios, G1 and G2, are not equal. An error trying to produce a shift in the output common-mode voltage is overridden by the common-mode control loop where the error becomes a balanced differential error around the output V_OCM.

The terms that create a differential error from a common-mode term and feedback ratio mismatch include the desired V_OCM voltage, any source common-mode voltage, any drift on the reference bias to the V_OCM control pin, any internal offset and drift in the V_OCM control path, and the input average bias current and drift.

Considering just the output common-mode control and the source common-mode voltage, the conversion to output differential offsets is through Equation 8.

Equation 8.

Neglecting any G1 and G2 mismatch because of standard values constraint, the conversion gain for these two terms can be recast in terms of the nominal R_F / R_G ≡ G and the tolerance T, as shown in Equation 9. When G increases, this conversion gain approaches 4T.

Equation 9.

This conversion gain to differential output error is applied to two error terms: V_OCM and the input bias current and drift. (The source common-mode voltage is assumed to be 0 V. If not, apply this gain to the source common-mode voltage and any resulting shift in application.)

The output error is applied to V_OCM, assuming that the input control pin is driven and not floating. The input bias current and drift are multiplied by the average R_F value then by the conversion gain to differential output error to create an added output differential error.

As an example of using these terms to estimate the worst-case output 25°C error band and then the worst-case drift (by adding all error terms together independently), use the gain of 1-V/V configuration with R_F = 1 kΩ and assume a ±1% tolerance on the resistors with the standard values used in Figure 9-9.

Figure 9-9 DC-Coupled Gain of 1 with R_F = 1 kΩ and Single-to-Differential Matched Input 50-Ω Impedance

The standard value constraint on the non-signal input side actually produces more gain mismatch than the resistor tolerances. For Figure 9-9, G2 = 1000 / 1020 = 0.9804 and G1 = 1000 / 1025.6 = 0.9751 nominally, then with a ±2% tolerance around the initial gain mismatch resulting from the standard values available if 1% resistors are used.

Using the maximum 25°C error terms and nominal resistor values with an exact 2.5-V input to the VOCM control pin gives Table 9-2, gains to the output differential error (V_OD), and then the summed output error band at 25°C. The output error is clearly dominated by the V_OCM voltage and the effect of the nominal feedback dividers being slightly mismatched. This analysis does not include resistor tolerances but the approach is the same with the wider error bands on the gain terms. Using 1% tolerance on the resistors setting the gain matching dominates the output error band through the V_OCM input voltage. For the lowest output error, this analysis shows that an exact match on the feedback dividers with precision resistors is preferred. However, doing so would require duplicating the exact network on the non-signal input side and the signal input side. Where input impedance matching is not required, the two R_G resistors are simply single equal resistors and the gain mismatch is just from the tolerance of the resistors.

The 0.00268 conversion gain for the gain ratio mismatch is the worst-case ratio starting from the initially lower G1 value resulting from the standard value constraint and using a ±1% tolerance on the R_F and R_G elements of the ratio. Adding in the resistor tolerances to the gain mismatch term greatly increases the contribution of those terms.

Normally, the expected drift in the output V_OD is of more interest than an initial error band. Table 9-3 shows these terms for the RGT package and the summed results by adding all terms independently to obtain a worst-case drift.

In Table 9-3, the input offset voltage drift dominates the output drift. For the last term, the drift for the V_OCM path is just for the internal offset drift of the common-mode path with a driven input. Any added external drift on the source of the V_OCM input must also be considered. This type of calculation can be repeated for the exact application circuit considering each of these terms in the context of a specific design.

The absolute accuracy and drift for the THS4551 are exceptionally good. Mismatched resistor feedback ratios combined with a high drift in the V_OCM control input can actually dominate the output V_OD drift. Where the output differential precision is more important than the input matching accuracy, consider matching the networks on the two sides of the input to obtain improved nominal G1 to G2 match. The gains for the input bias current error terms are relatively low when using the 1-kΩ feedback values. Higher R_F values provide the input-current-related drift terms more gain.