Table 5. Design Parameters

9.2.1.2.1 Input Common-Mode Voltage Range

The input common-mode voltage of a fully-differential op amp is the voltage at the + and – input pins of the op amp.

It is important to not violate the input common-mode voltage range (V_ICR) of the op amp. Assuming the op amp is in linear operation the voltage across the input pins is only a few millivolts at most. So finding the voltage at one input pin determines the input common-mode voltage of the op amp.

Treating the negative input as a summing node, the voltage is given by Equation 1:

Equation 1.

To determine the V_ICR of the op amp, the voltage at the negative input is evaluated at the extremes of V_OUT+.

As the gain of the op amp increases, the input common-mode voltage becomes closer and closer to the input common-mode voltage of the source.

9.2.1.2.2 Setting the Output Common-Mode Voltage

The output common-mode voltage is set by the voltage at the CM pin(s). The internal common-mode control circuit maintains the output common-mode voltage within 3-mV offset (typical) from the set voltage, when set within 0.5 V of midsupply, with less than 4-mV differential offset voltage. If left unconnected, the common-mode set point is set to midsupply by internal circuitry, which may be overdriven from an external source. Figure 82 is representative of the CM input. The internal CM circuit has about 700 MHz of –3-dB bandwidth, which is required for best performance, but it is intended to be a DC bias input pin. Bypass capacitors are recommended on this pin to reduce noise at the output. The external current required to overdrive the internal resistor divider is given by Equation 2:

Equation 2.

where

• V_CM is the voltage applied to the CM pin

Figure 82. CM Input Circuit

9.2.1.2.3 Single-Supply Operation (3 V to 5 V)

To facilitate testing with common lab equipment, the THS4509 EVM allows split-supply operation, and the characterization data presented in this data sheet were taken with split-supply power inputs. The device can easily be used with a single-supply power input without degrading the performance. Figure 83, Figure 84, and Figure 85 show DC and AC-coupled single-supply circuits with single-ended inputs. These configurations all allow the input and output common-mode voltage to be set to midsupply allowing for optimum performance. The information presented here can also be applied to differential input sources.

In Figure 83, the source is referenced to the same voltage as the CM pin (V_CM). V_CM is set by the internal circuit to midsupply. R_T along with the input impedance of the amplifier circuit provides input termination, which is also referenced to V_CM.

Figure 83. THS4509 DC-Coupled Single-Supply With Input Biased to V_CM

In Figure 84 the source is referenced to ground and so is the input termination resistor. R_PU is added to the circuit to avoid violating the V_ICR of the op amp. The proper value of resistor to add can be calculated from Equation 3:

Equation 3.

Figure 84. THS4509 DC-Coupled Single-Supply With R_PU Used to Set V_IC

V_IC is the desired input common-mode voltage, V_CM = CM, and R_IN = R_G+ R_S || R_T. To set to midsupply, make the value of R_PU = R_G+ R_S || R_T.

Table 6 is a modification of Table 3 to add the proper values with R_PU assuming a 50-Ω source impedance and setting the input and output common-mode voltage to midsupply.

There are two drawbacks to this configuration. One is that it requires additional current from the power supply. Using the values shown for a gain of 10 dB requires 37 mA more current with 5-V supply, and 22-mA more current with 3-V supply.

The other drawback is that this configuration also increases the noise gain of the circuit. In the 10-dB gain case, noise gain increases by a factor of 1.5.

Figure 85 shows AC coupling to the source. Using capacitors in series with the termination resistors allows the amplifier to self-bias both input and output to midsupply.

Figure 85. THS4509 AC-Coupled Single-Supply

9.2.1.2.4 THS4509 and ADS5500 Combined Performance

The THS4509 is designed to be a high-performance drive amplifier for high-performance data converters like the ADS5500 14-bit 125-MSPS ADC. Figure 86 shows a circuit combining the two devices, and Figure 87 shows the combined SNR and SFDR performance versus frequency with –1-dBFS input signal level sampling at 125 MSPS. The THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5500. The 100-Ω resistors and 2.7-pF capacitor between the THS4509 outputs and ADS5500 inputs along with the input capacitance of the ADS5500 limit the bandwidth of the signal to 115 MHz (–3 dB). For testing, a signal generator is used for the signal source. The generator is an ac-coupled 50-Ω source. A band-pass filter is inserted in series with the input to reduce harmonics and noise from the signal source. Input termination is accomplished through the 69.8-Ω resistor and 0.22-μF capacitor to ground in conjunction with the input impedance of the amplifier circuit. A 0.22-μF capacitor and 49.9-Ω resistor is inserted to ground across the 69.8-Ω resistor and 0.22-μF capacitor on the alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348-Ω feedback resistor. Refer to Table 6 for component values to set proper 50-Ω termination for other common gains. A split power supply of +4 V and –1 V is used to set the input and output common-mode voltages to approximately midsupply while setting the input common-mode of the ADS5500 to the recommended +1.55 V. This configuration maintains maximum headroom on the internal transistors of the THS4509 to insure optimum performance.

Figure 86. THS4509 and ADS5500 Circuit

Figure 87. THS4509 and ADS5500 SFDR and SNR Performance vs Frequency

Figure 88 shows the two-tone FFT of the THS4509 and ADS5500 circuit with 65-MHz and 70-MHz input frequencies. The SFDR is 90 dBc.

Figure 88. THS4509 and ADS5500 2-Tone FFT With 65-MHz and 70-MHz Inputs

9.2.1.2.5 THS4509 and ADS5424 Combined Performance

Figure 89 shows the THS4509 driving the ADS5424 ADC, and Figure 90 shows the combined SNR and SFDR performance versus frequency with –1-dBFS input signal level and sampling at 80 MSPS.

As before, the THS4509 amplifier provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5424. Input termination and circuit testing is the same as described above for the THS4509 and ADS5500 circuit.

The 225-Ω resistors and 2.7-pF capacitor between the THS4509 outputs and ADS5424 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to about 100MHz (–3 dB).

Because the ADS5424 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a single power-supply input with V_S+ = 5 V and V_S– = 0 V (ground).

Figure 89. THS4509 and ADS5424 Circuit