9.3.1 Differential to Single-Ended Stage (D2S) With Fixed Gain of 2-V/V (Pins 2, 3, 6 and 14)

This buffered-amplifier stage isolates the DAC output nodes from the differential to single-ended conversion. Presenting two high-impedance inputs allows the DAC to operate in its best configuration independent of subsequent operations. The two very wideband input buffers hold an approximately constant response shape over a wide input common-mode operating voltage. Figure 13 shows 6 dB of gain with 0.5-dB flatness through 500 MHz over the intended –1-to +3-V input common-mode range. In this case, the VREF pin is grounded, forcing the D2S output to be centered on ground for any input common-mode voltage. For the D2S-only tests, a 100-Ω load is used to showcase the performance of this stage directly driving a doubly-terminated cable. The wide input common-mode range of the D2S satisfies the required compliance voltage over a wide range of DAC types. Most current sourcing DACs require an average dc compliance voltage on their outputs near ground. Current sinking DACs require an average dc compliance voltage near their positive supply voltage for the analog section. The 3-V maximum common-mode range is intended to support DAC supplies up to 3.3 V, where the average output operating current pulls down from 3.3 V by the termination impedance from the supply. For instance, a 20-mA tail current DAC must level shift from a 3.3-V bias on the output resistors down to 3 V or lower. This DAC-to-THS3217 configuration requires at least a 300-mV dc level shift with half the tail current in each side, implying a 30-Ω load impedance to the supply on each side of the 20-mA reference current.

The overriding limits to the input common-mode operating range are due to the input buffer headroom. Over temperature, the D2S input headroom specification is 2 V to the negative supply and 1.5 V to the positive supply. Therefore, operation at a 3-V input common-mode voltage requires at least a 4.5-V positive supply, where 5 V is a more conservative minimum.

While DAC outputs rarely have any common-mode signal present (unless the reference current is being modulated), the D2S does a reasonable job of rejecting input common-mode signals over frequency. Figure 17 shows the CMRR to decrease above 10 MHz. For current-sinking DACs coming from a positive supply voltage, any noise on the positive supply looks like an input common-mode signal. Keeping the noise small at higher frequencies reduces the possibility of feedthrough to the D2S output due to the decreasing CMRR at higher frequencies. A current-sinking DAC uses pull-up resistors to the voltage supply to convert the DAC output current to a voltage. Make sure that the DAC voltage supply has been properly decoupled through a ferrite bead and capacitor, π-filter network similar to the supply decoupling for the THS3217 shown in Figure 90.

The D2S provides a differential gain of 6 dB. The gain is reasonably precise using internal resistor matching with extremely low gain drift over temperature (see Figure 61 and Figure 62). The single-ended D2S output signal can be placed over a wide range of dc offset levels using the VREF pin. The VREF pin shows a precise gain of 1 V/V to the D2S output. Grounding VREF places the first stage output centered on ground (with some offset voltage). For best ac performance through the D2S, anything driving the VREF pin must have a very wide bandwidth with very low output impedance over frequency while driving a 150-Ω load. The on-chip midscale buffer provides these features (see Figure 51). When a dc offset (or other small-level ac signal) must be applied to the VREF pin, buffer the signal through the midscale buffer stage. Maintain the total range of the dc offset plus signal swing within the available output swing range of the D2S. The headroom to the supplies is a symmetric ±1.65 V (max) over temperature. Therefore, on the minimum ±4-V supply, the D2S operates over a ±2.35-V output range. At the maximum ±7.9-V supply, a ±6.25-V output range is supported. At the higher swings, account for available linear output current, including the current into the internal feedback resistor load of approximately 500-Ω.

Figure 76 shows the internal structure of the D2S functional block. It consists of two internal stages:

1. The first stage consists of two wideband, closed-loop, fixed gain of 1 V/V buffers to isolate the requirements of the complementary DAC output from the difference operation of the D2S.
2. The second stage is a wideband CFA configured as a difference amplifier, operating in a fixed gain of 2 V/V, performing the differential to single-ended conversion.

Figure 76. D2S Operating Example

The CFA design offers the best, full-power bandwidth versus supply current, with moderate noise and dc precision. Figure 76 shows a typical current-sourcing DAC with a 20-mA total tail current. The tail current is split equally between the 25-Ω termination resistors to produce a dc common-mode voltage and a differential ac current signal. This example sets the input common-mode voltage at 0.25 V, and is also the compliance voltage of the DAC. The 25-Ω termination resistors shown here are typically realized as a 50-Ω matched reconstruction (or Nyquist) filter between the DAC and the THS3217 buffer inputs for most AWG applications. The DAC signal is further amplified by 6 dB in the second stage for a net transimpedance gain of 100-Ω to the D2S output at VO1. This configuration produces a 2-V_PP output for the 20-mA reference current assumed in the example of Figure 76. The input common-mode voltage is cancelled on the two sides of the op amp circuit to give a ground referenced output. Any voltage applied to the VREF pin has a gain transfer function of 1 V/V to VO1, independent of the signal path, as long as the source impedance of VREF is very low at dc and over frequency.

The IN+ buffer output drives a 150-Ω load with VREF grounded. Any source driving VREF must have the ability to drive a 150-Ω load with low output impedance across frequency. For differential input signals, the IN– buffer drives a 150-Ω active load. The active load is realized by a combination of the 250-Ω R_G resistor and the inverted and attenuated signal present at the inverting terminal of the difference amplifier stage. If only IN– is driven (with IN+ at a dc fixed level), the load is 250 Ω.

The resistor values around the D2S difference amplifier are derived in the following sequence, as shown in Figure 77:

1. Select the feedback resistor value to set the response shape for the wideband CFA stage. The 500-Ω design used here was chosen as a compromise between loading and noise constraints.
2. Set the input resistor on the inverting input side to give the desired single-sided gain for that path. Setting R_G= 250-Ω results in a gain of –2 V/V from the buffered signal (–V) to the output of the difference amplifier.
3. Solve the required attenuation to the noninverting input to get a matched gain magnitude for the signal provided at the buffer output (+V) on the noninverting path. If α = R2 / (R1 + R2), as shown in Figure 77, then the solution for α is shown in Equation 2:
Equation 1.
Equation 2.
Figure 77. D2S Impedance Analysis
4. After solving the attenuation from the buffer output to the amplifier noninverting input, set the impedance (R1 + R2). It is preferable to have the two first stage buffer outputs drive the same load impedance to match nonlinearity in their outputs in order to improve even-order harmonic distortion. The load impedance from –V to R_G has an active impedance because of the inverted and attenuated version of the input signal appearing at the inverting amplifier node from the +V input signal. Assuming a positive input signal into the +V path, an attenuated version of the signal appears at the amplifier summing junction side of R_G, while the inverted version of the signal appears on the input side of R_G.

The impedance seen at node –V in Figure 77 is derived in Equation 3 by solving for the V/I expression across R_G.

Equation 3.

For load balancing, (R1 + R2) = 150 Ω while the attenuation is α. More generally, all the terms are now available to solve for R2, as shown in Equation 4:

Equation 4.

R1 is then simply (Z_i- R2) = 50 Ω.

This analysis for matched gains and buffer loads can be applied to a more general discrete design using different target gains and starting R_F values. It is clearly useful to have the attenuation and buffer loading accurately controlled. Therefore, it is very important to control the impedance at the VREF pin to be as low as possible. For instance, using the midscale buffer to drive the VREF pin only adds 0.21 Ω dc impedance in series with R2. This low dc output impedance can only be delivered with a closed-loop buffer design. For discrete implementations of this D2S, consider the BUF602 buffer and LMH6702 wideband CFA amplifier. For even better dc and ac output impedance in the buffers (and possibly better gain), use a closed-loop, dual, wideband op amp like the OPA2889 for lower frequency applications, or the OPA2822 for higher frequency. These unity gain stable op amps can be used as buffers offering different performance options along with the LMH6702 wideband CFA over the design point chosen for the THS3217.

After gain matching is achieved in the single op amp differential stage, the common-mode input voltage is cancelled to the output, and the VREF input voltage is amplified by 1 V/V to the output. The analysis circuit is shown in Figure 78, where VREF is shown grounded at the R2 element.

Figure 78. D2S Common-Mode Cancellation

The gain magnitudes are equal on each side of the differential inputs; therefore, the common-mode inputs achieve the same gain magnitude, but opposite phase, resulting in common-mode signal cancellation. The inverting path gain is V_CM × (R_F / R_G). The noninverting path gain is V_CM × α × (1 + R_F / R_G). Using Equation 5:

Equation 5.

the noninverting path gain becomes +V_CM × R_F / R_G, and adding that result to the inverting path signal cancels to zero. Slight gain mismatches reduce this rejection to the 55-dB typical CMRR, with a 47-dB tested minimum. The 47-dB minimum over the 3-V maximum common mode input range adds another ±13.4-mV worst-case D2S output offset term to the specified maximum ±35-mV output offset with 0-V input common-mode voltage. The polarity of the gain mismatch is random.

The VREF pin input voltage (V_REF) generates a gain of 1 V/V using the analysis shown in Figure 79

Figure 79. Gain Transfer Function from VREF to VO1

The gain from VREF to VO1 is shown in Equation 6:

Equation 6.

Getting both R1 and (R1 + R2) in terms of R_G and the target attenuation, α simplifies, as shown in Equation 7:

Equation 7.

Putting Equation 7 back into the gain expression(Equation 6), and expanding out gives:

Equation 8.

Recall that in order to get differential gain balance, α = –(R_F / R_G). Putting that into Equation 8 reduces the expression to V_O1 = V_REF, a gain of 1 V/V. This gain is very precise as shown in the D2S Electrical Characteristics table, where the tested dc limits are 0.985 V/V to 1.015 V/V.

The D2S output offset and drift are largely determined by the internal elements. The only external consideration is the dc source impedance at the two buffer inputs. With low source impedance, the D2S output offset is tested to be within ±35 mV, that becomes a maximum ±17 mV input differential offset specification. Assuming the dc source impedances are closely matched, the mismatch in the two input bias currents adds another input offset term for higher source impedances. The input bias offset current is limited in test to be < ±0.40 µA. This error term does not rise to add more than ±1 mV input differential offset until the dc source impedance exceeds 2.5 kΩ. A high dc source impedance most commonly occurs in an input ac-coupled, single-supply application, where dc offsets are less critical.

The absolute input bias currents modifies the common-mode input voltage if the dc source resistance is too large. That term is tested to a limit of ±4 µA on each input. To move the input common mode voltage by ±100 mV, the dc source impedance must exceed 25 kΩ. This added input common-mode voltage is cancelled by the D2S at the output (VO1, pin6).

The D2S output noise is largely fixed by the internal elements. The D2S shows a differential input voltage noise of 9 nV/√Hz, and a current noise of 2 pA/√Hz on each input. Higher termination resistors increase this source noise, as given by Equation 9, where R_t is the dc termination impedance at each buffer input. The D2S has a 1/f corner at approximately 30 kHz (see Figure 18).

Equation 9.

The total differential input noise is dominated by the differential voltage noise. For instance, evaluating this expression for R_t = 200 Ω on each input, increases the total differential input noise to 9.4.nV/√Hz, only slightly greater than the 9 nV/√Hz for the D2S with 0-Ω source R_t on each input. If higher final output SNR is desired, consider generating as much input swing as the DAC can support, but increase the termination impedance. It is possible that a lower tail current with higher R_t will yield improved SNR at the D2S input. This differential input noise appears at the D2S output times a gain of 2 V/V.

Equation 10.

9.3.2 Midscale (DC) Reference Buffer (Pin 1 and Pin 15)

This optional block can be completely unconnected and not used if the design does not require this feature. Internal 50-kΩ resistors to the power supplies bias the input of the buffer to the midpoint of the supplies used. The internal resistors set a midsupply operating point when the buffer is not used, as well as a default midsupply point at the buffer output to be used in other stages for single-supply, ac-coupled applications.

The buffer provides a very wideband, low output-impedance when used to drive the VREF pin (see Figure 51). To provide this low broadband impedance, the closed-loop midscale (dc) reference buffer offers a very broadband SSBW, but only a modest large-signal bandwidth (LSBW); see Figure 49. This path is not normally intended to inject a wideband signal, but can be used for lower-amplitude signals. Driving the buffer output into the VREF pin allows a wideband small-signal term to be added into the D2S along with the signal from the differential inputs.

The midscale (or dc) reference buffer injects an offset voltage to the output offset of the D2S when it drives the VREF pin. The offset has very low drift, but consider the effect of the input bias current times the dc source impedance at VMID_IN (pin 1). When used as a default midsupply reference for single-supply operation, the input to this buffer is just the average of the total power supplies though a 25-kΩ source impedance. Add an external capacitor to filter the supply and the 50-kΩ internal resistors. A 1-µF capacitor on pin 1 adds a 6-Hz pole to the noise sources. If lower noise at lower frequencies is required, implement a midscale divider with external, lower-valued resistors in parallel with the internal 50-kΩ values.

If the midscale buffer drive the VREF pin, another noise term is added to Equation 9 and Equation 10. The midscale buffer 4.4-nV/√Hz voltage noise is amplified by 0 dB, and adds (RMS) a negligible impact to the total D2S output noise. The biggest impact comes when the internal default 50-kΩ dividers are used. Be sure to decouple pin 1 with at least a 1-µF capacitor in the application to reduce the noise contribution through this path. Figure 80 is the simulation circuit where the only change is to add or remove the 1-µF capacitor.

Figure 80. Midscale Buffer Noise Model

Figure 81 shows the simulated output noise for the midscale buffer using the internal 50-kΩ divider with and without a 1-µF capacitor on pin 1.

Figure 81. Buffer-Output Noise Comparison With and Without the 1-µF Bypass Capacitor on Pin 1

In the flat region, the 1-µF capacitor reduces the midscale buffer output spot noise from approximately 55 nV/√Hz to 4.4 nV/√Hz. If the noise below 100 Hz is unacceptable, either add a low-noise buffer to drive this input, or add lower-value resistors externally to set up the midsupply bias. Also, consider the noise impact of any reference voltage source driving the midscale buffer path.

9.3.3 Output Power Stage (OPS) (Pins 4, 7, 9, 10, 11, and 12)

This wideband current-feedback amplifier (CFA) provides a flexible output driver with several unique features. The OPS can be left unused if the specific application only uses the D2S alone, or a combination of the D2S with an off-chip power driver. If left unused, simply tie DISABLE (pin 10) and PATHSEL (pin 4) to the positive supply. This logic configuration turns the OPS off and opens up the external and internal OPS noninverting input paths. An internal fixed 18.5-kΩ resistor holds the external input pin at the logic reference voltage on pin 7. Additionally, the OPS output is connected to the inverting input through another internal 18.5-kΩ resistor when no external resistors are installed on pins 9, 11, or 12. Disabling the OPS saves approximately 21 mA of supply current from the nominal total 54 mA with all stages operating on ±6-V supplies.

The noninverting input to the OPS provides two possible paths controlled by the PATHSEL logic control, pin 4. With the logic reference (pin 7) at ground, floating pin 4 or controlling it to a voltage < 0.7 V connects the input path directly to the internal D2S output. Tying pin 4 to the positive supply, or controlling it to a logic level > 1.3 V, connects the input path to the external input at pin 9. The intent for this switched input is to allow an external filter to be inserted between the D2S output and OPS inputs when needed, and bypass the filter when not. Alternatively, this switched input also allows a completely different signal path to be inserted at the OPS input, independent of that available at the internal D2S output.

In situations where the D2S output at pin 6 is switched into another off-chip power driver, the OPS can be disabled using pin 10. With the logic reference (pin 7) at ground, floating pin 10, or controlling it to a voltage < 0.7 V, enables the OPS. Tying pin 10 to the positive supply, or controlling it to a logic level > 1.3 V, disables the OPS.

Operation of the wideband, current-feedback OPS requires an external feedback resistor and a gain element. After configuring, the OPS can amplify the D2S output through either the noninverting path, or be configured as an inverting amplifier stage using the external OPS input at pin 9 as a dc reference.

One of the first considerations when designing with the OPS is determining the external resistor values as a function of gain in order to hold the best ac performance. The loop gain (LG) of a CFA is set by the internal open-loop transimpedance gain from the inverting error current to the output, and the effective feedback impedance to the inverting input. The nominal internal open-loop transimpedance gain and phase are shown in Figure 82.

Figure 82. Simulated OPS Z_OL Gain And Phase

The feedback transimpedance (Z_OPT) can be approximated as shown in Equation 11, where R_i is the open-loop, high-frequency impedance into the inverting node of the OPS. For a detailed derivation of Equation 11, see Setting Resistor Values to Optimize Bandwidth section in the OPA695 datasheet (SBOS293).

Equation 11.

As the signal gain is varied, hold Z_OPT approximately constant to hold the ac response constant over gain. Holding Z_OPT constant is a requirement to solve for R_F. An example of the THS3217 OPS R_F derivation is shown in Equation 12:

Equation 12.

The calculations are complicated by the internal feedback resistor value of approximately 18.5-kΩ. After the external R_F is approximately set by the constant bandwidth consideration, the R_G must be set considering the other gain error terms. From the noninverting input of a CFA op amp, the total gain to the output includes a loss through the input buffer stage (described by the CMRR) and the loop gain (LG) loss set by the typical dc open-loop transimpedance gain and the feedback transimpedance. Extract the buffer gain from the VIN+ input to the VIN– input from the CMRR using Equation 13. This gain loss only applies to the noninverting mode of operation and can be neglected in inverting mode operation.

Equation 13.

The OPS has a typical CMRR of 49 dB (buffer gain, β = 0.9965) with a tested minimum of 47 dB (minimum buffer gain of 0.9955). The dc LG adds to the gain error. The LG is given by Equation 14 where the typical design gain of 2.5 V/V value is also shown (the 245 Ω shown for R_F is the external 249-Ω feedback resistor in parallel with the internal 18.5-kΩ feedback resistor).

Equation 14.

The closed-loop output impedance with a heavy load also adds a minor gain loss that is neglected here. The total noninverting gain is then set by Equation 15 (remember to include the internal R_F in this analysis. The R_F’ shown here is the parallel combination of the internal and external feedback resistors).

Equation 15.

Using nominal values for each term at the specified R_F = 249 Ω and R_G = 162 Ω gives the gain calculation in Equation 16, yielding a nominal gain very close to 2.5 V/V.

Equation 16.

Testing the total gain spread with the internal variation in buffer gain, open-loop transimpedance gain, internal feedback resistor, and ±1% external resistor variation gives a worst-case gain spread of 2.49 V/V to 2.51 V/V. The gain error is primarily dominated by the external 1% resistors. For the tighter tolerance shown in Table 2, use 0.1% precision resistors.

At very low gains (< 1.5 V/V) parasitic LC effects at the inverting input render a flat frequency response impossible. Looking then at gains from 1.5 V/V and up, a table of nominally recommended R_F and R_G values is shown in Table 2. Do not operate the OPS in noninverting gains of less than 2.5 V/V for large output signals because the limited slew-rate of the CFA input buffer causes signal degradation. Table 2 accounts for the nominal gain losses described previously, and uses standardized resistor values to minimize the nominal gain-error to target gain. The calculation also restricts the solution to a minimum R_G = 20 Ω. The gain calculations include the nominal buffer gain loss, the loop-gain effect, and the nominal internal feedback resistor = 18.5 kΩ.

The measured bandwidths in Table 2 come from Figure 25 using the resistor values in the table and a 100-Ω load. Plotting the R_F value versus gain gives the curve of Figure 83. The curve shows some ripple due to the standard value resistors used to minimize the target dc gain error.

Figure 83. Suggested External R_F Value vs Noninverting Gain for the OPS

Using R_F values greater than the recommended values in Table 2 band-limits the response, whereas using less than the recommended R_F values peaks the response. Using the values shown in Table 2 results in an approximately constant SSBW (see Figure 25. Holding a more constant loop-gain over the external gain setting also acts to hold a more constant output impedance profile, as shown in Figure 84. The swept-frequency, closed-loop, output impedance is shown for gains of 2.5 V/V, 5 V/V, and 10 V/V using the R_F and R_G values of Table 2. The first two steps do a good job of delivering the same (and very low) output impedance over frequency, while the gain of 10 V/V shows the expected higher closed-loop output impedance due to the reduced loop-gain and bandwidth.

Figure 84. OPS Closed-Loop Output Impedance vs Gain Setting

Reducing the R_F value with increasing gain also helps minimize output noise versus a fixed R_F design. See Figure 39 for the three noise terms for the OPS. The total output noise calculation is shown in Equation 17:

Equation 17.

where

• R_S is the source impedance on the noninverting input. If the OPS is driven from the D2S stage directly using the internal path, R_S ≈ 0 Ω.
• NG = (1 + R_F / R_G) for the design point.
• The flat-band noise numbers for the OPS are:
  • E_ni = 3.2 nV/√Hz
  • I_bn = 2.7 pA/√Hz
  • I_bi = 30 pA/√Hz

Using the values of R_F and R_G listed in Table 2, a swept gain output- and input-referred noise estimate is computed, as shown in Table 3. In this sweep, R_S = 0 Ω. The input-referred noise (E_ni) in Table 2 is at the noninverting input of the OPS. To refer the noise to the D2S differential inputs, divide the output noise by two if there is no interstage loss. Dividing the E_ni column by 2 V/V shows that the OPS noise contribution is negligible when referred to the D2S inputs, where the 9-nV/√Hz differential input noise dominates. Operating with higher feedback resistors in the OPS quickly increases the output noise due to the inverting input current noise term. Although increasing R_F improves phase margin (for example, when driving a capacitive load), be careful to check the total output noise using Equation 17.

Operating the OPS as an inverting amplifier is also possible. When driving the OPS directly from the D2S to the R_G resistor, use the values shown in Table 2 for the noninverting mode to achieve good results. Note that the R_G resistor is the load for the D2S stage. Operating with the D2S driving an R_G < 80 Ω increases the harmonic distortion of the D2S. In that case, scaling R_F and R_G up to reduce the loading may result in better system performance at the cost of a lower OPS bandwidth. Driving the D2S output at pin 6 into the OPS in an inverting mode allows for the option to select the external input of the OPS, and drive another signal or dc level into the noninverting input at pin 9. In order to reduce layout parasitics, consider splitting the R_G resistor in two, with the first half close to pin 6 and the second half close to pin 12. Splitting R_G in this manner places the trace capacitance inside the two resistors keeping both active nodes more stable. Also, open up the ground and power planes under the trace, if possible.

Using the PS to receive and amplify a signal in the inverting mode with a matched terminating impedance, requires another resistor to ground (R_M) along with R_G. This R_M resistor is shown in Figure 85 for a 50-Ω matched input impedance design.

Figure 85. Inverting OPS Operation With Matched Input Impedance

Table 4 gives the recommended external resistor values versus gain for the inverting gain mode with input matching configuration. Table 4 solves for the required R_F to simultaneously allow the gain, input impedance (50 Ω), and feedback transimpedance to be controlled to the optimum target values. The table includes the effect of the internal 18.5-kΩ feedback resistor, and minimizes the RMS error to input impedance target (Z_I) and overall gain.

At higher gains, R_M increases to larger values, and the resistor is excluded from the circuit. The resulting input impedance of the network is resistor R_G. From that point, R_F simply increases to get higher gains, thereby rapidly reducing the SSBW. However, below a gain of –5 V/V, the inverting design with the values shown in Table 4 holds a more constant SSBW versus the noninverting mode (see Figure 26).

9.3.3.1 Output DC Offset and Drift for the OPS

The OPS provides modest dc precision with typical and maximum dc error terms in Table 5. The input offset voltage applies to either input path with very little difference between the internal and external paths.

Table 5. Typical Offset and Bias Current Values for the OPS

PARAMETER	TYPICAL	MINIMUM	MAXIMUM	UNIT
VIO	±1	–12	12	mV
Ibn	5	–5	15	µA
Ibi	±5	–40	40	µA

Selecting the internal path results in no source resistance for I_bn, so that term drops out. When the external path is selected, a dc source impedance may be present, so the I_bn term creates another error term, and adds to the total output offset.

Stepping through an example design for the OPS output dc offset using the external path with a low insertion loss filter shown in Figure 92, along with its R_F and R_G values, gives the following results:

• R_S for the I_bn term = 34 Ω || 249 Ω = 30 Ω. (dc source impedance for the filter design)
• R_F including the internal 18.5 kΩ resistor = 249 Ω || 18.5 kΩ = 245.7 Ω
• Resulting gain with the 130-Ω R_G element = 2.89 V/V

Table 6 shows the typical and worst-case output error terms. Note that a positive current out of the noninverting input gives a positive output offset term, whereas a positive current out of the inverting input gives a negative output term.

Table 6. Output Offset Voltage Contribution From Various Error Terms at 25°C

ERROR TERM	TYPICAL	MINIMUM	MAXIMUM	UNIT
Ibn × RS × AV	0.433	–0.43	1.29	mV
VIO × AV	±2.89	–34.68	34.68	mV
Ibi × RF	±1.22	–9.83	9.83	mV
Total error	–3.67 to +4.54	–44.94	45.8	mV

The input offset voltage dominates the error terms. The worst-case numbers are calculated by adding the individual errors algebraically, but is rarely seen in practice. None of the OPS input dc error terms are correlated. To compute output drift numbers, use the same gains shown in Table 6 with the specified drift numbers.

The OPS PATHSEL control responds extremely quickly with low-switching glitches, as shown in Figure 86. For this test, the D2S input is set to GND, and the output of the D2S is connected to the external OPS input. The PATHSEL switch is then toggled at 10 MHz. The results show the offset between the internal and external paths as well matched.

Figure 86. OPS Path-Select Switching Glitch

The OPS includes a disable feature that reduces power consumption from approximately 21 mA to 2.4 mA. The logic controls are intended to be ground-referenced regardless of the power supplies used. The logic reference (GND, pin 7) is normally grounded and also provides a connection to the internal 18.5-kΩ resistor on pin 9 (default bias to pin 7). Operating in a single-supply configuration with –V_CC at GND and the external OPS input (pin 9) floated, places pin 9 internally at –V_CC = GND. Driving the external OPS input (pin 9) from a source within the operating range overrides the bias to –V_CC. However, if the application requires pin 9 to be floated in a single-supply operation, consider centering the voltage on pin 9 with an added 18.5-kΩ external resistor to the +V_CC supply.

If the disable feature is not needed, simply float or ground DISABLE (pin 10) to hold the OPS in the enabled state. Increasing the voltage on the DISABLE pin greater than 1.3 V disables the OPS and reduces the current to approximately 2.4 mA. If the OPS is unused in the application, it can be disabled by tying pin 10 to +V_CC, even up to the maximum operating supply of 15.8 V in a single-supply design.

Do not move the logic threshold away from those set by the logic ground at pin 7. If a different logic swing level is required, and pin 7 is biased to a different voltage, be sure the source can sink the typical 280 µA coming out of pin 7. Also recognize that the 18.5-kΩ bias resistor on the external OPS input (pin 9) is connected to pin 7 voltage internally.

As shown in Figure 56, the OPS enables in approximately 100 ns from the logic threshold at 1.0 V while disabling to a final value in approximately 500 ns.

9.3.3.3 Switch Feedthrough to the OPS

The OPS has two logic control pins, giving four combinations of states; therefore, various feedthrough effects must be considered. Figure 57 and Figure 58 show the feedthrough of the switches with the OPS disabled. With the OPS enabled, the signal feedthrough from the deselected input to the OPS output is shown in Figure 87 and Figure 88 at different closed-loop OPS gains. The results are shown for a 100-mV_PP signal at the deselected input and are not normalized to the gain of the OPS. Adding a low-pass filter between the DAC and the D2S inputs helps reduce the feedthrough at higher frequencies.

PATHSEL < 0.7 V,

100-mVPP signal to VIN (pin 9)

Figure 87. Forward Feedthrough With OPS Enabled, Internal Path Selected

PATHSEL > 1.3 V,

100-mVPP signal to VREF (pin 14) with D2S inputs grounded

Figure 88. Forward Feedthrough With OPS Enabled, External Path Selected

9.3.4 Digital Control Lines

The THS3217 provides two logic input lines that provide control over the input path to the OPS and the OPS power disable feature; both are referenced to GND (pin 7). The control logic defaults to a logic-low state when the pins are externally floated. Pin 7 must have a dc path to some reference voltage for correct operation. Float the two logic control lines to enable the OPS and select the internal path connecting the D2S internal output to the OPS noninverting input. Figure 89 shows a simplified internal schematic for either logic control input pin.

Figure 89. Logic Control Internal Schematic

The Q2 branch of the differential pair sets up a switch threshold approximately 1 V greater than the voltage applied to pin 7 (GND). If the control input is floating or < 0.7 V, the differential-pair tail current diverts to the 100-Ω detector load, and results in an output voltage (V_CTRL, shown in Figure 89) that activates the desired mode. The floated pin default voltage is the PNP base current into the 19-kΩ resistor. As the control pin voltage rises above 1.3 V, the differential-pair current is completely diverted away from the 100 Ω side, thus switching states.

This unique design allows the logic control inputs to be connected to a single-supply as high as 15.9 V, in order to hold the inputs permanently high, while still accepting a low ground-referenced logic swing for single-supply operation. The NPN transistor (Q3) and two diodes (D1 and D2) act as a clamp to prevent large voltages from appearing across the differential stage.

When the OPS is disabled, both input paths to the OPS are also opened up regardless of the state of PATHSEL (pin 4).

9.4.1 Full-Signal Path Mode

The full-signal path from the D2S to the OPS is available in various options. Three options are described in the following subsections.

9.4.1.1 Internal Connection With Fixed Common-Mode Output Voltage

The most basic operation is to ground the VREF pin, and use the internal connection from the D2S to the OPS to provide a differential to single-ended, high-power driver. Figure 90 shows the characterization circuit used for the combined performance specifications.

Figure 90. Differential to Single-Ended, Gain of 5-V/V Configuration

This configuration shows the test circuit used to generate Figure 1. Some of the key features in this basic configuration include:

1. The power supplies are brought into the OPS first, then back to the input stage through a π-filter comprised of a ferrite bead and local decoupling caps on –VCC2 and +VCC2, pins 5 and 16, respectively (see the Power Supply Recommendations section for more information).
2. The two logic lines are grounded. This logic configuration (with pin 7 grounded) selects the internal path from the D2S to OPS, and enables the OPS.
3. The external I/O pins of the midscale buffer are left floating.
4. The VREF pin is grounded, thus setting the D2S output common-mode voltage at VO1 (pin 6) to ground.
5. The D2S external output is loaded with a 200-Ω resistor to ground. Lighter loading on the VO1 pin (versus the 100 Ω used to characterize the D2S only) results in increased frequency response peaking. Heavier loading degrades the D2S distortion performance.
6. The external OPS input at pin 9 is left floating. However, it is internally tied to ground by the internal 18.5-kΩ resistor.
7. The feedback resistor in the OPS is set to the parallel combination of the external 249-Ω resistor and the internal 18.5-kΩ resistor. This 245.7-Ω total R_F with the 162-Ω R_G resistor gives a gain of approximately 2.5 V/V (7.98 dB) in the OPS stage
8. The input D2S gives a gain of 2 V/V (6 dB), and along with the 2.5 V/V (7.98 dB) from the OPS, gives an overall gain of 5 V/V (13.98 dB) with > 700 MHz of SSBW (see Figure 1).

9.4.1.2 Internal Connection With Adjustable Common-Mode Output Voltage

The simplest modification to this starting configuration is using the midscale buffer to drive the VREF pin with either a dc or ac source into VMID_IN (pin 1), shown in Figure 91.

Figure 91. Differential to Single-Ended, Gain of 5-V/V Configuration With VREF Driven by the Midscale Buffer

The VREF input can be used to offset the output of the D2S that will then be amplified by the OPS. The total dc offset at the output of the OPS can also be corrected by adjusting the voltage at VMID_IN (pin 1). The on-chip midscale buffer can be used as a low-impedance source to drive the correction voltage to the VREF pin. A wideband small-signal source can also be summed into this path with a gain of 1 V/V to the D2S output pin. Figure 49 shows the midscale buffer to have an extremely flat response through 100 MHz for < 100-mV_PPswings, while 1 V_PP can be supported through 80 MHz with a flat response.

From this point on, the diagrams are simplified to not show the power-supply elements. However, the supplies are required by any application, as described in the Application and Implementation section.

9.4.1.3 External Connection

In the configuration shown in Figure 92, the bias to PATHSEL (pin 4) is changed in order to select the external input of the OPS. The external D2S output drives a low insertion loss, third-order Bessel filter. The filter in this example is designed with a low frequency insertion loss of 1.2 dB and f_–3dB = 140 MHz, and results in an additional insertion loss of 1 dB at 100 MHz. The OPS gain is slightly increased to recover the filter loss, in order to give an input to output gain of 5 V/V. Using an interstage filter between the D2S and the OPS improves the step response by reducing the overshoot.

Figure 92. External Path Configuration With Interstage Low-Pass Filter

9.4.2 Dual-Output Mode

The D2S stage can also be used to directly drive a doubly-terminated line, as shown in Figure 93. In addition, the OPS amplifies the internal D2S output by 5 V/V. The internal path to the OPS is selected with PATHSEL (pin 4) at ground, and the OPS gain is increased to 5 V/V. A 2-V_PP output at VO1 produces a 10-V_PP output at VOUT (pin 11). This 10-V_PP swing requires higher supply operation to provide sufficient headroom in the OPS output stage in order to preserve signal integrity. A power supply of ±7.5 V provides adequate headroom.

Figure 93. Dual-Output Mode

A simple modification to the circuit in Figure 93 is to disable the OPS, and switch to the external input path by taking both logic lines (pin 4 and pin 10) high. The D2S output at VO1 is then used either directly or through a filter to an even higher power driver like the ±15-V THS3091.

9.4.3 Differential I/O Voltage Mode

Having two amplifiers available also allows a simple differential I/O implementation with independent output common-mode control, as shown in Figure 94. In this configuration, the D2S provides one side of the differential output, while simultaneously driving the OPS configured in an inverting gain of –1 V/V to provide the differential output on the other side. The output at VMID_OUT biases the external noninverting input, VIN+ (pin 9). This circuit configuration places the differential input to the output filter at a common-mode voltage, V_{MID_OUT}.

Figure 94. Differential I/O Configuration With Independent Output Common-Mode Voltage Control