SLLSFP9 February 2024 TCAN1465-Q1 , TCAN1469-Q1
ADVANCE INFORMATION
The TCAN146x-Q1 is a CAN FD signal improvement capable (SIC) transceiver supporting data rates up to 8Mbps meeting physical layer requirements of the ISO 11898-2:2024 Annex A for high speed CAN specification and the CiA 601-4 Signal Improvement (SIC) specification. The TCAN1465-Q1 and TCAN1469-Q1 support selective wake up on dedicated CAN-frames. The devices can also wake up via remote wake up using CAN bus implementing the ISO 11898-2:2024 Annex A for Wake Up Pattern (WUP). The TCAN146x-Q1 support 1.8V, 3.3V and 5V processors using VIO pin. The processor interface is through the SPI, RXD and TXD terminals. The devices have a Serial Peripheral Interface (SPI) that connects to a local microprocessor for configuration. SPI supports clock rates up to 4MHz. The serial data output (SDO) pin can be configured as an interrupt output pin when the chip select pin is high providing flexibility for system design.
The TCAN146x-Q1 provides CAN FD transceiver function: differential transmit capability to the bus and differential receive capability from the bus. The device includes many protection features providing device and CAN network robustness.
The CAN bus has two logical states during operation: recessive and dominant. See Figure 7-1 and Figure 7-2.
Recessive bus state is when the bus is biased to a common mode of about 2.5V via the high resistance internal input resistors of the receiver of each node on the bus across the termination resistors. Recessive is equivalent to logic high and is typically a differential voltage on the bus of almost 0V. Recessive state is also the idle state.
Dominant bus state is when the bus is driven differentially by one or more drivers. Current is induced to flow through the termination resistors and generate a differential voltage on the bus. Dominant is equivalent to logic low and is a differential voltage on the bus greater than the minimum threshold for a CAN dominant. A dominant state overwrites the recessive state.
During arbitration, multiple CAN nodes may transmit a dominant bit at the same time. In this case, the differential voltage of the bus is greater than the differential voltage of a single driver.
Transceivers have a third bus state where the bus terminals are weakly biased to ground via the high resistance internal resistors of the receiver. See Figure 7-1 and Figure 7-2.
The TCAN146x-Q1 provides many enhanced features that are provided in the Section 8.3 section. Enhanced features such as advanced bus fault detection, fail-safe, watchdog and providing a processor interrupt are described in their specific subsections.