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ZHCSPG1 December 2021 TCAN1164-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DMT|14
- MPSS087B

散熱焊盤機械數據 (封裝 | 引腳)

DMT|14
- QFND638

訂購信息

zhcspg1_oa

8.8 Switching Characteristics

Over recomended operating conditions with T_J = -40°C to 150°C, unless otherwise noted. All typical values are taken at 25°C, V_SUP = 12 V and R_L = 60 Ω

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
Supply Switching Characteristics
t_{POWER_UP}	CAN supply power up time		C_VCCOUT = 10 μF See Figure 9-9		1.8	4	ms
t_UV(SUP)	V_SUP filter time (rising and falling)			4		25	μs
t_UV(VCCOUT)	V_CCOUT filter time (rising and falling)		Time for device to enter sleep state reset state once UV_CCOUT is reached		30		μs
Device Switching Characteristics
t_UV(nRST)	Undervoltage detection delay time nRST low				10	50	μs
t_{WK_FILTER}	Bus time to meet filtered bus requirments for wakeup request		See Figure 10-15	0.5		1.8	μs
t_{WK_TIMEOUT}	Bus wakeup timeout value		See Figure 10-15	0.8		2	ms
t_SILENCE	Time out for bus inactivity				0.9	1.2	s
t_INACTIVE	Hardware timer for failsafe and power up inactivity⁽¹⁾			3	4	5	min
t_BIAS	Time from the start of a dominant-recessive-dominant sequence until Vsym ≥ 0.1		Each phase: 6 μs See Figure 9-10			250	μs
t_CAN(ACTIVE)	Time from switching to CAN active mode to transceiver ready to transmit		V_CCOUT > UV_VCCOUT(R)			25	us
t_PROP(LOOP1)	Total loop delay, driver input (TXD) to receiver output (RXD) Recessive to dominant		R_L = 60 ?, C_L = 100 pF, C_L(RXD) = 15 pF See Figure 9-6		100	160	ns
t_PROP(LOOP2)	Total loop delay, driver input (TXD) to receiver output (RXD) Dominant to recessive - TCAN1164-Q1		R_L = 60 ?, C_L = 100 pF, C_L(RXD) = 15 pF See Figure 9-6		120	175	ns
t_PROP(LOOP2)	Total loop delay, driver input (TXD) to receiver output (RXD) Dominant to recessive - TCAN1164T-Q1		R_L = 60 ?, C_L = 100 pF, C_L(RXD) = 15 pF See Figure 9-6		130	195	ns
t_{mode_slp_reset}	WUP or LWU event to INH asserted high, see					50	μs
Driver Switching Characteristics
t_pHR	Propagation delay time, high TXD to driver recessive	TCAN1164T-Q1	R_L = 60 ?, C_L = 100 pF, R_CM= open See Figure 9-2	65	82	130	ns
t_pLD	Propagation delay time, low TXD to driver dominant			25	50	110	ns
t_sk(p)	Pulse skew (\|t_pHR - t_pLD\|)				25	50	ns
t_R	Differential output signal rise time				40		ns
t_F	Differential output signal fall time				95		ns
t_pHR	Propagation delay time, high TXD to driver recessive	TCAN1164-Q1	R_L = 60 ?, C_L = 100 pF, R_CM= open See Figure 9-2	20	35	70	ns
t_pLD	Propagation delay time, low TXD to driver dominant			15	40	70	ns
t_sk(p)	Pulse skew (\|t_pHR - t_pLD\|)				10	20	ns
t_R	Differential output signal rise time				40		ns
t_F	Differential output signal fall time				45		ns
t_{TXD_DTO}	Dominant timeout		R_L = 60 ?, C_L = open See Figure 9-7, TXD = 0 V	1.2		3.8	ms
Receiver Switching Characteristics
t_pRH	Propagation delay time, bus recessive input to high RXD	TCAN1164T-Q1	C_L(RXD) = 15 pF See Figure 9-3	25	65	140	ns
t_pRH	Propagation delay time, bus recessive input to high RXD	TCAN1164-Q1	C_L(RXD) = 15 pF See Figure 9-3	25	80	140	ns
t_pDL	Propagation delay time, bus dominant input to RXD low output		C_L(RXD) = 15 pF See Figure 9-3	20	50	110	ns
t_R	Output signal rise time (RXD)		C_L(RXD) = 15 pF See Figure 9-3		8		ns
t_F	Output signal fall time (RXD)		C_L(RXD) = 15 pF See Figure 9-3		5		ns
nRST Characteristics
t_nRST	Minimum low time for reset		Input pulse width	15			μs
t_nRST(cold)	Output pulse width		Cold crank	20		27	ms
t_nRST(warm)	Output pulse width		Warm crank	1		1.5	ms
SPI Switching Characteristics
f_SCK	SCK, SPI clock frequency		Normal, standby, and silent modes			4	MHz
t_SCK	SCK, SPI clock period		Normal, standby, and silent modes; See Figure 9-12	250			ns
t_RSCK	SCK rise time		See Figure 9-11			40	ns
t_FSCK	SCK fall time		See Figure 9-11			40	ns
t_SCKH	SCK, SPI clock high		Normal, standby, and silent modes; See Figure 9-12	125			ns
t_SCKL	SCK, SPI clock low		Normal, standby, and silent modes; See Figure 9-12	125			ns
t_ACC	First read access time from chip select			50			ns
t_CSS	Chip select setup time		See Figure 9-11	100			ns
t_CSH	Chip select hold time		See Figure 9-11	100			ns
t_CSD	Chip select disable time		See Figure 9-11	50			ns
t_SISU	Data in setup time		Normal, standby, and silent modes; See Figure 9-11	50			ns
t_SIH	Data in hold time		Normal, standby, and silent modes; See Figure 9-11	50			ns
t_SOV	Data out valid		Normal, standby, and silent modes; See Figure 9-12			80	ns
t_RSO	SO rise time		See Figure 9-12			40	ns
t_FSO	SO fall time		See Figure 9-12			40	ns
CAN FD Timing Characteristics
t_BIT(BUS)	Bit time on CAN bus output pins with t_BIT(TXD) = 500 ns	TCAN1164-Q1	R_L = 60 ?, C_L = 100 pF C_L(RXD) = 15 pF Δt_REC = t_BIT(RXD) - t_BIT(BUS) See Figure 9-6	435		530	ns
	Bit time on CAN bus output pins with t_BIT(TXD) = 200 ns			155		210	ns
	Bit time on CAN bus output pins with t_BIT(TXD) = 125 ns			80		140	ns
t_BIT(BUS)	Bit time on CAN bus output pins with t_BIT(TXD) = 500 ns	TCAN1164T-Q1	R_L = 60 ?, C_L = 100 pF C_L(RXD) = 15 pF Δt_REC = t_BIT(RXD) - t_BIT(BUS) See Figure 9-6	450		530	ns
t_BIT(BUS)	Bit time on CAN bus output pins with t_BIT(TXD) = 200 ns	TCAN1164T-Q1		155		210	ns
t_BIT(RXD)	Bit time on RXD output pins with t_BIT(TXD) = 500 ns		R_L = 60 ?, C_L = 100 pF C_L(RXD) = 15 pF Δt_REC = t_BIT(RXD) - t_BIT(BUS) See Figure 9-6	400		550	ns
	Bit time on RXD output pins with t_BIT(TXD) = 200 ns			120		220	ns
	Bit time on RXD output pins with t_BIT(TXD) = 125 ns	TCAN1164-Q1		80		135	ns
Δt_REC	Receiver timing symmetry with t_BIT(TXD) = 500 ns		R_L = 60 ?, C_L = 100 pF C_L(RXD) = 15 pF Δt_REC = t_BIT(RXD) - t_BIT(BUS) See Figure 9-6	-50		20	ns
	Receiver timing symmetry with t_BIT(TXD) = 200 ns			-45		15	ns
	Receiver timing symetry with t_BIT(TXD) = 125 ns	TCAN1164-Q1		-40		10	ns

(1) Timer is reset when the CAN bus changes states.