ZHCSDP5E December 2010 – February 2017 TCA9554A
PRODUCTION DATA.
- 1 特性
- 2 應用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- DW|16
訂購信息
5 Pin Configuration and Functions
PW, DB, DBQ, or DW Package
16-Pin TSSOP, SSOP, SOIC
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| A0 | 1 | I | Address input. Connect directly to VCC or ground |
| A1 | 2 | I | Address input. Connect directly to VCC or ground |
| A2 | 3 | I | Address input. Connect directly to VCC or ground |
| GND | 8 | — | Ground |
| INT | 13 | O | Interrupt output. Connect to VCC through a pull-up resistor |
| P0 | 4 | I/O | P-port input-output. Push-pull design structure. At power on, P0 is configured as an input |
| P1 | 5 | I/O | P-port input-output. Push-pull design structure. At power on, P1 is configured as an input |
| P2 | 6 | I/O | P-port input-output. Push-pull design structure. At power on, P2 is configured as an input |
| P3 | 7 | I/O | P-port input-output. Push-pull design structure. At power on, P3 is configured as an input |
| P4 | 9 | I/O | P-port input-output. Push-pull design structure. At power on, P4 is configured as an input |
| P5 | 10 | I/O | P-port input-output. Push-pull design structure. At power on, P5 is configured as an input |
| P6 | 11 | I/O | P-port input-output. Push-pull design structure. At power on, P6 is configured as an input |
| P7 | 12 | I/O | P-port input-output. Push-pull design structure. At power on, P7 is configured as an input |
| SCL | 14 | I | Serial clock bus. Connect to VCC through a pull-up resistor |
| SDA | 15 | I/O | Serial data bus. Connect to VCC through a pull-up resistor |
| VCC | 16 | — | Supply voltage |