ZHCSJQ8C may 2019 – june 2023 TCA9548A-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- Application and Implementation
- Power Supply Recommendations
- 9 Layout
- 10Device and Documentation Support
- Mechanical, Packaging, and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
訂購信息
9.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA9548A-Q1 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
A power-on reset is shown in Figure 9-1.
Table 9-1 specifies the performance of the power-on reset feature for TCA9548A-Q1 for both types of power-on reset.
| PARAMETER | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| VCC_FT | Fall time | See Figure 9-1 | 1 | 100 | ms |
| VCC_RT | Rise time | See Figure 9-1 | 0.1 | 100 | ms |
| VCC_TRR | Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or when VCC drops to GND) | See Figure 9-1 | 40 | μs | |
| VCC_GH | Level that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1 μs | See Figure 9-2 | 1.2 | V | |
| VCC_GW | Glitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCC | See Figure 9-2 | 10 | μs | |
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 9-2 and Table 9-1 provide more information on how to measure these specifications.
Figure 9-2 Glitch Width and Glitch HeightVPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 9-3 and Table 9-1 provide more details on this specification.
Figure 9-3 VPOR Example