SCPS202C October 2009 – May 2016 TCA9539
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, the TCA9539 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
The voltage waveform for a power-on reset is shown in Figure 40.
Table 8 specifies the performance of the power-on reset feature for the TCA9539.
Table 8. Recommended Supply Sequencing and Ramp Rates (1)
| PARAMETER | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| VCC_FT | Fall rate | See Figure 40 | 0.1 | ms | ||
| VCC_RT | Rise rate | See Figure 40 | 0.1 | ms | ||
| VCC_TRR | Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV or when VCC drops to GND) | See Figure 40 | 1 | μs | ||
| VCC_GH | The level (referenced to VCC) that VCC can glitch down to, but not cause a functional disruption when VCC_GW | See Figure 41 | 1.2 | V | ||
| VCC_MV | The minimum voltage that VCC can glitch down to without causing a reset (VCC_GH must not be violated) | See Figure 41 | 1.5 | V | ||
| VCC_GW | Glitch width that will not cause a functional disruption | See Figure 41 | 10 | μs | ||
| VPORF | Voltage trip point of POR on falling VCC | 0.75 | 1 | V | ||
| VPORR | Voltage trip point of POR on rising VCC | 1.2 | 1.5 | V | ||
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 41 and Table 8 provide more information on how to measure these specifications.
Figure 41. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPORR is the voltage level at which the reset condition is released and all the registers and the I2C-SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 42 and Table 8 provide more details on this specification.
Figure 42. VPOR