ZHCSFH3A September 2016 – February 2023 TCA6408A-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Device and Documentation Support
- 11支持資源
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PW|16
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
9.3.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA6408A-Q1 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
Ramping up the device VCCP before VCCI is recommended to prevent SDA from potentially being stuck LOW.
The two types of power-on reset are shown in #SCPS2347834 and #SCPS2349418.
Figure 9-6 VCCP is Lowered Below 0.2 V and then Ramped Up to VCCP
Figure 9-7 VCCP is Lowered Below the POR Threshold, then Ramped Back Up to VCCPTable 9-1 specifies the performance of the power-on reset feature for TCA6408A-Q1 for both types of power-on reset.
| PARAMETER | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| tFT | Fall rate | See #SCPS2347834 | 0.1 | 2000 | ms | |
| tRT | Rise rate | See #SCPS2347834 | 0.1 | 2000 | ms | |
| tRR_GND | Time to re-ramp (when VCCP drops to GND) | See #SCPS2347834 | 1 | μs | ||
| tRR_POR50 | Time to re-ramp (when VCCP drops to VPOR_MIN – 50 mV) | See #SCPS2349418 | 1 | μs | ||
| VCCP_GH | Level that VCCP can glitch down from VCCP, but not cause a functional disruption when tVCCP_GW = 1 μs | See #SCPS2349110 | 1.2 | V | ||
| VCCP_MV | The minimum voltage that VCC can glitch down to without causing a reset (VCC_GH must not be violated) | See #SCPS2349110 | 1.5 | V | ||
| tVCCP_GW | Glitch width that does not cause a functional disruption when tVCCP_GH = 0.5 × VCCx | See #SCPS2349110 | 10 | μs | ||
| VPORF | Voltage trip point of POR on falling VCCP | 0.6 | 1 | V | ||
| VPORR | Voltage trip point of POR on rising VCCP | 1.2 | 1.5 | V | ||
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (tVCCP_GW) and height (VCCP_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. #SCPS2349110 and Table 9-1 provide more information on how to measure these specifications.
Figure 9-8 Glitch Width and Glitch HeightVPOR is critical to the power-on reset. VPORR / VPORF is the voltage level at which the reset condition is released/asserted and all the registers and the I2C/SMBus state machine are initialized to the default states (upon a release of a reset condition). The voltage that the device has a reset condition asserted or released differs based on whether VCCP is being lowered to or from 0. #SCPS2341389 and Table 9-1 provide more details on this specification.
Figure 9-9 Power On Reset