ZHCSCU3C January 2014 – September 2019 TCA5013
PRODUCTION DATA.
When the voltage on the VDD pin falls below the VDDTH the INT_SUPL bit (bit[2] of Reg 0x41) and The STAT_SUPL bit (bit[1], Reg 0x10) are both set to 1 and the INT pin is asserted low. The INT_SUPL bit is cleared and the INT pin is released when the interrupt status register is read. The STAT_SUPL bit clears when the fault condition goes away, that is, VDD > VDDTH