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ZHCSG71 March 2017 TAS6424L-Q1

PRODUCTION DATA.

封裝選項(xiàng)

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
PVDD, VBAT	DC supply voltage relative to GND		–0.3	30	V
V_MAX	Transient supply voltage: PVDD, VBAT	t ≤ 400 ms exposure	–1	40	V
V_RAMP	Supply-voltage ramp rate: PVDD, VBAT			75	V/ms
VDD	DC supply voltage relative to GND		–0.3	3.5	V
I_MAX	Maximum current per pin (PVDD, VBAT, OUT_xP, OUT_xM, GND)			±8	A
I_{MAX_PULSED}	Pulsed supply current per PVDD pin (one shot)	t < 100 ms		±12	A
V_LOGIC	Input voltage for logic pins (SCL, SDA, SDIN1, SDIN2, MCLK, BCLK, LRCLK, MUTE, STANDBY, I2C_ADDRx)		–0.3	VDD + 0.5	V
V_GND	Maximum voltage between GND pins			±0.3	V
T_J	Maximum operating junction temperature		–55	150	°C
T_stg	Storage temperature		–55	150	°C

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100–002⁽¹⁾		±3000	V
		Charged-device model (CDM), per AEC Q100–011	All pins	±500
		Charged-device model (CDM), per AEC Q100–011	Corner pins (1, 28, 29 and 56)	±1000

(1) AEC Q100–002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS–001 specification.

7.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
PVDD	Output FET supply voltage	Relative to GND	4.5		18	V
VBAT	Battery supply voltage input	Relative to GND	4.5	14.4	18	V
VDD	DC logic supply	Relative to GND	3.0	3.3	3.5	V
T_A	Ambient temperature		–40		125	°C
T_J	Junction temperature	An adequate thermal design is required	–40		150	°C
R_L	Nominal speaker load impedance	BTL Mode	2	4		Ω
R_L	Nominal speaker load impedance	PBTL Mode	1	2		Ω
R_{PU_I2C}	I²C pullup resistance on SDA and SCL pins		1	4.7	10	kΩ
C_Bypass	External capacitance on bypass pins	Pin 2, 3, 5, 6, 8, 9, 10, 19		1		µF
C_OUT	External capacitance to GND on OUT pins	Limit set by DC-diagnostic timing		1	3.3	µF
L_O	Output filter inductance	Minimum inductance at I_SD current levels	1			µH

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TAS6424L-Q1⁽²⁾	TAS6424L-Q1⁽³⁾	UNIT
		DKQ (HSSOP)	DKQ (HSSOP)
		56 PINS	56 PINS
R_θJA	Junction-to-ambient thermal resistance	—	—	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	0.7	1.1	°C/W
R_θJB	Junction-to-board thermal resistance	—	—	°C/W
ψ_JT	Junction-to-top characterization parameter	—	—	°C/W
ψ_JB	Junction-to-board characterization parameter	10	10	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—	—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

(2) JEDEC Standard 4 Layer PCB.

(3) Measured using the TAS6424L-Q1 EVM layout and heat sink. The device is not intended to be used without a heat sink.

7.5 Electrical Characteristics

Test conditions (unless otherwise noted): T_C = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, R_L = 4 Ω, P_out = 1 W/ch, ƒ = 1 kHz, f_SW = 2.11 MHz, AES17 Filter, default I²C settings, see Figure 59 and Figure 62

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OPERATING CURRENT
I_{PVDD_IDLE}	PVDD idle current	All channels playing, no audio input		75	90	mA
I_{VBAT_IDLE}	VBAT idle current	All channels playing, no audio input		90	100	mA
I_{PVDD_STBY}	PVDD standby current	STANDBYActive, VDD = 0 V		1	10	μA
I_{VBAT_STBY}	VBAT standby current	STANDBYActive, VDD = 0 V		4	10	μA
I_VDD	VDD supply current	All channels playing, –60-dB signal		15	18	mA
OUTPUT POWER
P_{O_BTL}	Output power per channel, BTL	4 Ω, PVDD = 14.4 V, THD+N = 1%, T_C = 75°C	20	22		W
		4 Ω, PVDD = 14.4 V, THD+N = 10%, T_C = 75°C	25	27
		2 Ω, PVDD = 14.4 V, THD+N = 1%, T_C = 75°C	20	22
		2 Ω, PVDD = 14.4 V, THD+N = 10%, T_C = 75°C	25	27
		4 Ω, PVDD = 18 V, THD+N = 1%, T_C = 75°C	30	33
		4 Ω, PVDD = 18 V, THD+N = 10%, T_C = 75°C	40	45
P_{O_PBTL}	Output power per channel in parallel mode, PBTL	2 Ω, PVDD = 14.4 V, THD+N = 1%, T_C = 75°C	35	40		W
		2 Ω, PVDD = 14.4 V, THD+N = 10%, T_C = 75°C	45	50
		1 Ω, PVDD = 14.4 V, THD+N = 1%, T_C = 75°C	50	52
		1 Ω, PVDD = 14.4 V, THD+N = 10%, T_C = 75°C	60	62
		2 Ω, PVDD = 18 V, THD+N = 1%, T_C = 75°C	60	65
		2 Ω, PVDD = 18 V, THD+N = 10%, T_C = 75°C	75	80
EFF_P	Power efficiency	4 channels operating, 25-W output power/ch 4-Ω load, PVDD = 14.4 V, T_C = 25°C, including indcutor losses⁽¹⁾		86%
AUDIO PERFORMANCE
V_n	Output noise voltage	Zero input, A-weighting, gain level 1, PVDD = 14.4 V		42		μV
		Zero input, A-weighting, gain level 2, PVDD = 14.4 V		55
		Zero input, A-weighting, gain level 3, PVDD = 18 V		67
		Zero input, A-weighting, gain level 4, PVDD = 25 V		85
GAIN	Peak output voltage/dBFS	Gain level 1, Register 0x01, bit 1-0 = 00		7.5		V/FS
		Gain level 2, Register 0x01, bit 1-0 = 01		15
		Gain level 3, Register 0x01, bit 1-0 = 10		21
		Gain level 4, Register 0x01, bit 1-0 = 11		29
Crosstalk	Channel crosstalk	PVDD = 14.4 Vdc + 1 V_RMS, ƒ = 1 kHz		-90	-75	dB
PSRR	Power-supply rejection ratio	PVDD = 14.4 Vdc + 1 V_RMS, ƒ = 1 kHz		75		dB
THD+N	Total harmonic distortion + noise			0.02%	0.05%
G_CH	Channel-to-channel gain variation		–0.5	0	0.5	dB
LINE OUTPUT PERFORMANCE
V_{n_LINEOUT}	LINE output noise voltage	Zero input, A-weighting, channel set to LINE MODE		42		μV
V_{O_LINEOUT}	LINE output voltage	0-dB input, channel set to LINE MODE		5.5		V_RMS
THD+N	Line output total harmonic distortion + noise	V_O = 2 V_RMS , channel set to LINE MODE		0.01%	0.03%
DIGITAL INPUT PINS
V_IH	Input logic level high		70			%VDD
V_IL	Input logic level low				30	%VDD
I_IH	Input logic current, high	V_I = VDD			15	µA
I_IL	Input logic current, low	V_I = 0			–15	µA
PWM OUTPUT STAGE
R_DS(on)	FET drain-to-source resistance	Not including bond wire and package resistance		90		mΩ
OVERVOLTAGE (OV) PROTECTION
V_{PVDD_OV}	PVDD overvoltage shutdown		19.3	20	22	V
V_{PVDD_OV_HYS}	PVDD overvoltage shutdown hysteresis			0.8		V
V_{VBAT_OV}	VBAT overvoltage shutdown		19.3	20	22	V
V_{VBAT_OV_HYS}	VBAT overvoltage shutdown hysteresis			0.6		V
UNDERVOLTAGE (UV) PROTECTION
VBAT_UV	VBAT undervoltage shutdown			4	4.5	V
VBAT_{UV_HYS}	VBAT undervoltage shutdown hysteresis			0.2		V
PVDD_UV	PVDD undervoltage shutdown			4	4.5	V
PVDD_{UV_HYS}	PVDD undervoltage shutdown hysteresis			0.2		V
BYPASS VOLTAGES
V_GVDD	Gate drive bypass pin voltage			7		V
V_AVDD	Analog bypass pin voltage			6		V
V_VCOM	Common bypass pin voltage			2.5		V
V_VREG	Regulator bypass pin voltage			5.5		V
POWER-ON RESET (POR)
V_POR	VDD voltage for POR			2.1	2.7	V
V_{POR_HY}	VDD POR recovery hysteresis voltage			0.5		V
OVERTEMPERATURE (OT) PROTECTION
OTW(i)	Channel overtemperature warning			150		°C
OTSD(i)	Channel overtemperature shutdown			175		°C
OTW	Global junction overtemperature warning	Set by register 0x01 bit 5-6, default value		130		°C
OTSD	Global junction overtemperature shutdown			160		°C
OT_HYS	Overtemperature hysteresis			15		°C
LOAD OVER CURRENT PROTECTION
I_LIM	Overcurrent cycle-by-cycle limit	OC Level 1	3	3		A
I_LIM	Overcurrent cycle-by-cycle limit	OC Level 2	4.2	4.8		A
I_SD	Overcurrent shutdown	OC Level 1, Any short to supply, ground, or other channels		6		A
I_SD	Overcurrent shutdown	OC Level 2, Any short to supply, ground, or other channels		7		A
MUTE MODE
G_MUTE	Output attenuation			100		dB
CLICK AND POP
V_CP	Output click and pop voltage	ITU-R 2k filter, High-Z/MUTE to Play, Play to Mute/High-Z		7		mV
DC OFSET
V_OFFSET	Output offset voltage			2	5	mV
DC DETECT
DC_FAULT	Output DC fault protection			2	2.5	V
DIGITAL OUTPUT PINS
V_OH	Output voltage for logic level high	I = ±2 mA	90			%VDD
V_OL	Output voltage for logic level low	I = ±2 mA			10	%VDD
t_{DELAY_CLIPDET}	Signal delay when output clipping detected				20	μs
LOAD DIAGNOSTICS
S2P	Maximum resistance to detect a short from OUT pins to PVDD				500	Ω
S2G	Maximum resistance to detect a short from OUT pins to ground				200	Ω
SL	Shorted load detection tolerance	Other channels in Hi-Z			±0.5	Ω
OL	Open load	Other channels in Hi-Z	40	70		Ω
T_{DC_DIAG}	DC diagnostic time	All 4 Channels		230		ms
LO	Line output				6	kΩ
T_{LINE_DIAG}	Line output diagnostic time			40		ms
AC_IMP	AC impedance accuracy	Gain linearity, ƒ = 19 kHz, R_L = 2 Ω to 16 Ω,		25%
AC_IMP	AC impedance accuracy	Offset		±0.5		Ω
T_{AC_DIAG}	AC diagnostic time	All 4 Channels		520		ms
I2C_ADDR PINS
t_{I2C_ADDR}	Time delay needed for I²C address set-up			300		μs

Tested with Output Inductor DFEG7030D-3R3M.

7.6 Timing Requirements

Test conditions (unless otherwise noted): T_C = 25 °C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, R_L = 4 Ω, P_O = 1 W/ch, ƒ = 1 kHz, f_SW = 2.11 MHz, AES17 Filter, default I²C settings, see Figure 59 and Figure 62

			MIN	TYP	MAX	UNIT
I²C CONTROL PORT (See Figure 22)
t_BUS	Bus free time between start and stop conditions		1.3			μs
t_HOLD1	Hold time, SCL to SDA		0			ns
t_HOLD2	Hold time, start condition to SCL		0.6			μs
t_START	I²C startup time after VDD power on reset				12	ms
t_RISE	Rise time, SCL and SDA				300	ns
t_FALL	Fall time, SCL and SDA				300	ns
t_SU1	Setup, SDA to SCL		100			ns
t_SU2	Setup, SCL to start condition		0.6			μs
t_SU3	Setup, SCL to stop condition		0.6			μs
t_W(H)	Required pulse duration SCL High		0.6			μs
t_W(L)	Required pulse duration SCL Low		1.3			μs
SERIAL AUDIO PORT (See Figure 16)
D_MCLK, D_SCLK	Allowable input clock duty cycle		45%	50%	55%
ƒ_MCLK	Supported MCLK frequencies: 128, 256, or 512		128		512	xFS
ƒ_{MCLK_Max}	Maximum frequency				25	MHz
t_SCY	SCLK pulse cycle time		40			ns
t_SCL	SCLK pulse-with LOW		16			ns
t_SCH	SCLK pulse-with HIGH		16			ns
t_rise/fall	Rise and fall time		4			ns
t_SF	SCLK rising edge to FSYNC edge		8			ns
t_FS	FSYNC rising edge to SCLK edge		8			ns
t_DS	DATA set-up time		8			ns
t_DH	DATA hold time		8			ns
c_i	Input capacitance, pins MCLK, SCLK, FSYNC, SDIN1, SDIN2				10	pF
T_LA	Latency from input to output measured in FSYNC sample count	FSYNC = 44.1 kHz or 48 kHz			30
T_LA	Latency from input to output measured in FSYNC sample count	FSYNC = 96 kHz			12

7.7 Typical Characteristics

T_A = 25 ºC, V_VDD = 3.3 V, VBAT = PVDD = 14.4 V, R_L = 4 Ω, f_IN = 1 kHz, f_s = 48 kHz, f_SW = 2.1 MHz, AES17 filter, default I²C settings, see Figure 59 and Figure 62 (unless otherwise noted)