ZHCSO75A June 2021 – November 2021 TAS6424E-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Options
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 Recommended Operating Conditions
- 7.3 ESD Ratings
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Typical Characteristics: Bridge-Tied Load (BTL)
- 7.7 Typical Characteristics: Bridge-Tied Load (BTL, 384 kHz)
- 7.8 Typical Characteristics: Parallel Bridge-Tied (PBTL)
- 7.9 Typical Characteristics: Parallel Bridge-Tied Load (PBTL, 384 kHz)
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Serial Audio Port
- 9.3.2 DC Blocking
- 9.3.3 Volume Control and Gain
- 9.3.4 High-Frequency Pulse-Width Modulator (PWM)
- 9.3.5 EMI Management Features
- 9.3.6 Gate Drive
- 9.3.7 Power FETs
- 9.3.8 Load Diagnostics
- 9.3.9
Protection and Monitoring
- 9.3.9.1 Overcurrent Limit (ILIMIT)
- 9.3.9.2 Overcurrent Shutdown (ISD)
- 9.3.9.3 DC Detect
- 9.3.9.4 Clip Detect
- 9.3.9.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
- 9.3.9.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
- 9.3.9.7 Undervoltage (UV) and Power-On-Reset (POR)
- 9.3.9.8 Overvoltage (OV) and Load Dump
- 9.3.10 Power Supply
- 9.3.11 Hardware Control Pins
- 9.4 Device Functional Modes
- 9.5 Programming
- 9.6
Register Maps
- 9.6.1 Mode Control Register (address = 0x00) [default = 0x00]
- 9.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
- 9.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
- 9.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
- 9.6.5 Channel State Control Register (address = 0x04) [default = 0x55]
- 9.6.6 Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]
- 9.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
- 9.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
- 9.6.9 DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
- 9.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
- 9.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
- 9.6.12 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
- 9.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
- 9.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
- 9.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
- 9.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
- 9.6.17 Warnings Register (address = 0x13) [default = 0x20]
- 9.6.18 Pin Control Register (address = 0x14) [default = 0x00]
- 9.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
- 9.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
- 9.6.21 AC Load Diagnostic Impedance Report Ch1 through Ch4 Registers (address = 0x17–0x1A) [default = 0x00]
- 9.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
- 9.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
- 9.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
- 9.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
- 9.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
- 9.6.27 Clip Control Register (address = 0x22) [default = 0x01]
- 9.6.28 Clip Window Register (address = 0x23) [default = 0x14]
- 9.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
- 9.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
- 9.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
- 9.6.32 Miscellaneous Control 5 Register (address = 0x28) [default = 0x0A]
- 9.6.33 Spread-Spectrum Control 1 Register (address = 0x77) [default = 0x00]
- 9.6.34 Spread Spectrum Control 2 Register (address = 0x78) [default = 0x3F]
- 9.6.35 Spread Spectrum Control 3 Register (address = 0x79) [default = 0x00]
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
9.5.5 Random Read
As shown in Figure 9-12, a single-byte data-read transfer begins with the primary device transmitting a start condition followed by the I2C device address and the R/W bit. For the data-read transfer, both a write followed by a read occur. Initially, a write occurs to transfer the address byte or bytes of the internal memory address to be read. As a result, the R/W bit is a 0. After receiving the address and the R/W bit, the device responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the primary device transmits another start condition followed by the address and the R/W bit again. This time the R/W bit is a 1, indicating a read transfer. After receiving the address and the R/W bit, the device again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address being read. After receiving the data byte, the primary device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.
Figure 9-12 Random Read Transfer