ZHCSJM6A April 2019 – October 2019 TAS6421-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 說(shuō)明（續(xù)）
- 6 Device Options
- 7 Pin Configuration and Functions
- 8 Specifications
- 9 Parameter Measurement Information
-
10Detailed description
- 10.1 Overview
- 10.2 Functional Block Diagram
- 10.3
Feature Description
- 10.3.1 Serial Audio Port
- 10.3.2 DC Blocking
- 10.3.3 Volume Control and Gain
- 10.3.4 High-Frequency Pulse-Width Modulator (PWM)
- 10.3.5 Gate Drive
- 10.3.6 Power FETs
- 10.3.7 Load Diagnostics
- 10.3.8
Protection and Monitoring
- 10.3.8.1 Overcurrent Limit (ILIMIT)
- 10.3.8.2 Overcurrent Shutdown (ISD)
- 10.3.8.3 DC Detect
- 10.3.8.4 Clip Detect
- 10.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
- 10.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
- 10.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)
- 10.3.8.8 Overvoltage (OV) and Load Dump
- 10.3.9 Power Supply
- 10.3.10 Hardware Control Pins
- 10.4 Device Functional Modes
- 10.5 Programming
- 10.6
Register Maps
- 10.6.1 Mode Control Register (address = 0x00) [default = 0x00]
- 10.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
- 10.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
- 10.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
- 10.6.5 Channel State Control Register (address = 0x04) [default = 0x55]
- 10.6.6 Channel 1 Volume Control Register (address = 0x05) [default = 0xCF]
- 10.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
- 10.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
- 10.6.9 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
- 10.6.10 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
- 10.6.11 Channel State Reporting Register (address = 0x0F) [default = 0x40]
- 10.6.12 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
- 10.6.13 Global Faults 1 Register (address = 0x11) [default = 0x00]
- 10.6.14 Global Faults 2 Register (address = 0x12) [default = 0x00]
- 10.6.15 Warnings Register (address = 0x13) [default = 0x20]
- 10.6.16 Pin Control Register (address = 0x14) [default = 0x00]
- 10.6.17 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
- 10.6.18 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
- 10.6.19 AC Load Diagnostic Impedance Report Ch1 Register (address = 0x17) [default = 0x00]
- 10.6.20 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
- 10.6.21 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
- 10.6.22 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
- 10.6.23 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
- 10.6.24 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
- 10.6.25 Clip Control Register (address = 0x22) [default = 0x01]
- 10.6.26 Clip Window Register (address = 0x23) [default = 0x14]
- 10.6.27 Clip Warning Register (address = 0x24) [default = 0x00]
- 10.6.28 ILIMIT Status Register (address = 0x25) [default = 0x00]
- 10.6.29 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
- 11Application and Implementation
- 12Power Supply Recommendations
- 13Layout
- 14器件和文檔支持
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DKQ|56
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DKQ|56
訂購(gòu)信息
10.5.2 I2C Bus Protocol
The device has a bidirectional serial-control interface that is compatible with the Inter IC (I2C) bus protocol and supports 100 kbps and 400 kbps data transfer rates for random and sequential write and read operations. The TAS6421-Q1 device is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status.
The I2C bus uses two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The device holds SDA LOW during the acknowledge-clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. The number of bytes that can be transmitted between start and stop conditions is unlimited. When the last word transfers, the master generates a stop condition to release the bus.
Figure 30. Typical I2C Sequence 
Figure 31. SCL and SDA Timing Use the I2C ADDRx pins to program the device slave address. Read and write data can be transmitted using single-byte or multiple-byte data transfers.