ZHCSBC4D May   2013  – May 2017 TAS5760MD

PRODUCTION DATA.  

1. 1 特性
2. 2 應用
3. 3 說明
4. 4 修訂歷史記錄
5. 5 Device Comparison Table
6. 6 Pin Configuration and Functions
7. 7 Specifications
   1. 7.1  Absolute Maximum Ratings
   2. 7.2  ESD Ratings
   3. 7.3  Recommended Operating Conditions
   4. 7.4  Thermal Information
   5. 7.5  Digital I/O Pins
   6. 7.6  Master Clock
   7. 7.7  Serial Audio Port
   8. 7.8  Protection Circuitry
   9. 7.9  Speaker Amplifier in All Modes
   10. 7.10 Headphone Amplifier and Line Driver
   11. 7.11 I²C Control Port
   12. 7.12 Typical Idle, Mute, Shutdown, Operational Power Consumption
8. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagram
   3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
      2. 8.3.2 Speaker Amplifier Audio Signal Path
         1. 8.3.2.1 Serial Audio Port (SAP)
            1. 8.3.2.1.1 I²S Timing
            2. 8.3.2.1.2 Left-Justified
            3. 8.3.2.1.3 Right-Justified
         2. 8.3.2.2 DC Blocking Filter
         3. 8.3.2.3 Digital Boost and Volume Control
         4. 8.3.2.4 Digital Clipper
         5. 8.3.2.5 Closed-Loop Class-D Amplifier
      3. 8.3.3 Speaker Amplifier Protection Suite
         1. 8.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin)
         2. 8.3.3.2 DC Detect Protection
      4. 8.3.4 Headphone and Line Driver Amplifier
   4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Control Mode
         1. 8.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
         2. 8.4.1.2 Serial Audio Port in Hardware Control Mode
         3. 8.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
         4. 8.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
         5. 8.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
         6. 8.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
         7. 8.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
         8. 8.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
            1. 8.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
      2. 8.4.2 Software Control Mode
         1. 8.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin)
         2. 8.4.2.2 Serial Audio Port Controls
            1. 8.4.2.2.1 Serial Audio Port (SAP) Clocking
         3. 8.4.2.3 Parallel Bridge Tied Load Mode via Software Control
         4. 8.4.2.4 Speaker Amplifier Gain Structure
            1. 8.4.2.4.1 Speaker Amplifier Gain in Software Control Mode
            2. 8.4.2.4.2 Considerations for Setting the Speaker Amplifier Gain Structure
            3. 8.4.2.4.3 Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode
         5. 8.4.2.5 I²C Software Control Port
            1. 8.4.2.5.1 Setting the I²C Device Address
            2. 8.4.2.5.2 General Operation of the I²C Control Port
            3. 8.4.2.5.3 Writing to the I²C Control Port
            4. 8.4.2.5.4 Reading from the I²C Control Port
   5. 8.5 Register Maps
      1. 8.5.1 Control Port Registers - Quick Reference
      2. 8.5.2 Control Port Registers - Detailed Description
         1. 8.5.2.1  Device Identification Register (0x00)
         2. 8.5.2.2  Power Control Register (0x01)
         3. 8.5.2.3  Digital Control Register (0x02)
         4. 8.5.2.4  Volume Control Configuration Register (0x03)
         5. 8.5.2.5  Left Channel Volume Control Register (0x04)
         6. 8.5.2.6  Right Channel Volume Control Register (0x05)
         7. 8.5.2.7  Analog Control Register (0x06)
         8. 8.5.2.8  Reserved Register (0x07)
         9. 8.5.2.9  Fault Configuration and Error Status Register (0x08)
         10. 8.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
         11. 8.5.2.11 Digital Clipper Control 2 Register (0x10)
         12. 8.5.2.12 Digital Clipper Control 1 Register (0x11)
9. 9 Application and Implementation
   1. 9.1 Application Information
   2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Using Software Control
         1. 9.2.1.1 Design Requirements
         2. 9.2.1.2 Detailed Design Procedure
            1. 9.2.1.2.1 Startup Procedures- Software Control Mode
            2. 9.2.1.2.2 Shutdown Procedures- Software Control Mode
            3. 9.2.1.2.3 Component Selection and Hardware Connections
               1. 9.2.1.2.3.1 I²C Pullup Resistors
               2. 9.2.1.2.3.2 Digital I/O Connectivity
            4. 9.2.1.2.4 Recommended Startup and Shutdown Procedures
            5. 9.2.1.2.5 Headphone and Line Driver Amplifier
               1. 9.2.1.2.5.1 Charge-Pump Flying Capacitor and DR_VSS Capacitor
               2. 9.2.1.2.5.2 Decoupling Capacitors
               3. 9.2.1.2.5.3 Gain-Setting Resistor Ranges
               4. 9.2.1.2.5.4 Using the Line Driver Amplifier in the TAS5760MD as a Second-Order Filter
               5. 9.2.1.2.5.5 External Undervoltage Detection
               6. 9.2.1.2.5.6 Input-Blocking Capacitors
            6. 9.2.1.2.6 Gain-Setting Resistors
         3. 9.2.1.3 Application Curve
      2. 9.2.2 Stereo BTL Using Hardware Control
         1. 9.2.2.1 Design Requirements
         2. 9.2.2.2 Detailed Design Procedure
            1. 9.2.2.2.1 Startup Procedures- Hardware Control Mode
            2. 9.2.2.2.2 Shutdown Procedures- Hardware Control Mode
            3. 9.2.2.2.3 Digital I/O Connectivity
         3. 9.2.2.3 Application Curve
      3. 9.2.3 Mono PBTL Using Software Control
         1. 9.2.3.1 Design Requirements
         2. 9.2.3.2 Detailed Design Procedure
            1. 9.2.3.2.1 Startup Procedures- Software Control Mode
            2. 9.2.3.2.2 Shutdown Procedures- Software Control Mode
            3. 9.2.3.2.3 Component Selection and Hardware Connections
               1. 9.2.3.2.3.1 I²C Pull-Up Resistors
               2. 9.2.3.2.3.2 Digital I/O Connectivity
         3. 9.2.3.3 Application Curve
      4. 9.2.4 Mono PBTL Using Hardware Control
         1. 9.2.4.1 Design Requirements
         2. 9.2.4.2 Detailed Design Procedure
            1. 9.2.4.2.1 Startup Procedures- Hardware Control Mode
            2. 9.2.4.2.2 Shutdown Procedures- Hardware Control Mode
            3. 9.2.4.2.3 Component Selection and Hardware Connections
            4. 9.2.4.2.4 Digital I/O Connectivity
         3. 9.2.4.3 Application Curve
10. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
11. 11Layout
    1. 11.1 Layout Guidelines
       1. 11.1.1 General Guidelines for Audio Amplifiers
       2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
       3. 11.1.3 Optimizing Thermal Performance
          1. 11.1.3.1 Device, Copper, and Component Layout
          2. 11.1.3.2 Stencil Pattern
             1. 11.1.3.2.1 PCB Footprint and Via Arrangement
                1. 11.1.3.2.1.1 Solder Stencil
    2. 11.2 Layout Example
12. 12器件和文檔支持
    1. 12.1 文檔支持
       1. 12.1.1 相關文檔
    2. 12.2 社區資源
    3. 12.3 商標
    4. 12.4 靜電放電警告
    5. 12.5 Glossary
13. 13機械、封裝和可訂購信息