SLAS988B June 2014 – August 2015 TAS5756M
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 MCLK Timing
- 7.7 Serial Audio Port Timing - Slave Mode
- 7.8 Serial Audio Port Timing - Master Mode
- 7.9 I2C Bus Timing - Standard
- 7.10 I2C Bus Timing - Fast
- 7.11 SPK_MUTE Timing
- 7.12 Power Dissipation
- 7.13 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Power-on-Reset (POR) Function
- 8.3.2 Device Clocking
- 8.3.3
Serial Audio Port
- 8.3.3.1 Clock Master Mode from Audio Rate Master Clock
- 8.3.3.2 Clock Master from a Non-Audio Rate Master Clock
- 8.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
- 8.3.3.4 Clock Slave Mode with SLCK PLL to Generate Internal Clocks (3-Wire PCM)
- 8.3.3.5 Serial Audio Port - Data Formats and Bit Depths
- 8.3.3.6 Input Signal Sensing (Power-Save Mode)
- 8.3.3.7 Serial Data Output
- 8.3.4 Modulation Scheme
- 8.3.5 miniDSP Audio Processing Engine
- 8.3.6 Adjustable Amplifier Gain and Switching Frequency Selection
- 8.3.7
Error Handling and Protection Suite
- 8.3.7.1 Device Overtemperature Protection
- 8.3.7.2 SPK_OUTxx Overcurrent Protection
- 8.3.7.3 DC Offset Protection
- 8.3.7.4 Internal VAVDD Undervoltage-Error Protection
- 8.3.7.5 Internal VPVDD Undervoltage-Error Protection
- 8.3.7.6 Internal VPVDD Overvoltage-Error Protection
- 8.3.7.7 External Undervoltage-Error Protection
- 8.3.7.8 Internal Clock Error Notification (CLKE)
- 8.3.8 GPIO Port and Hardware Control Pins
- 8.3.9 I2C Communication Port
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1 2.0 (Stereo BTL) System
- 9.2.2 Mono (PBTL) Systems
- 9.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems
- 9.2.4 2.2 (Dual Stereo BTL) Systems
- 9.2.5 1.1 (Dual BTL, Bi-Amped) Systems
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DCA|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DCA|48
訂購(gòu)信息
10 Power Supply Recommendations
10.1 Power Supplies
The TAS5756M device requires two power supplies for proper operation. A high-voltage supply called PVDD is required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one low-voltage power supply called DVDD is required to power the various low-power portions of the device. The allowable voltage range for both the PVDD and the DVDD supply are listed in the Recommended Operating Conditions table.
Figure 84. Power Supply Functional Block Diagram
10.1.1 DVDD Supply
The DVDD supply required from the system is used to power several portions of the device. As shown in the Figure 84, it provides power to the DVDD pin, the CPVDD pin, and the AVDD pin. Proper connection, routing, and decoupling techniques are highlighted in the TAS5756M device EVM User's GuideSLAU583 (as well as the Application and Implementation section and Layout Example section) and must be followed as closely as possible for proper operation and performance. Deviation from the guidance offered in the TAS5756M device EVM User's Guide, which followed the same techniques as those shown in theApplication and Implementation section, may result in reduced performance, errant functionality, or even damage to the TAS5756M device.
Some portions of the device also require a separate power supply which is a lower voltage than the DVDD supply. To simplify the power supply requirements for the system, the TAS5756M device includes an integrated low-dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD supply and its output is presented on the DVDD_REG pin, providing a connection point for an external bypass capacitor. It is important to note that the linear regulator integrated in the device has only been designed to support the current requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the device.
The outputs of the high-performance DACs used in the TAS5756M device are ground centered, requiring both a positive low-voltage supply and a negative low-voltage supply. The positive power supply for the DAC output stage is taken from the AVDD pin, which is connected to the DVDD supply provided by the system. A charge pump is integrated in the TAS5756M device to generate the negative low-voltage supply. The power supply input for the charge pump is the CPVDD pin. The CPVSS pin is provided to allow the connection of a filter capacitor on the negative low-voltage supply. As is the case with the other supplies, the component selection, placement, and routing of the external components for these low voltage supplies are shown in the TAS5756MDCAEVM and should be followed as closely as possible to ensure proper operation of the device.
10.1.2 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are highlighted in the TAS5756MDCAEVM and must be followed as closely as possible for proper operation and performance. Due the high-voltage switching of the output stage, it is particularly important to properly decouple the output power stages in the manner described in the TAS5756M device EVM User's Guide. Lack of proper decoupling, like that shown in the EVM User's Guide, results in voltage spikes which can damage the device.
A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD_REG pin is provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note that the linear regulator integrated in the device has only been designed to support the current requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the device.