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ZHCSEX0A March 2016 – March 2016 TAS5733L

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DCA|48
- MPDS044E

散熱焊盤機械數據 (封裝 | 引腳)

DCA|48
- PPTD094K

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		VALUE	UNIT
Supply voltage	DVDD, AVDD	–0.3 to 3.6	V
Supply voltage	PVDD	–0.3 to 20	V
Input voltage	3.3-V digital input	–0.5 to DVDD + 0.5	V
	5-V tolerant⁽²⁾ digital input (except MCLK)	–0.5 to DVDD + 2.5⁽⁴⁾
	5-V tolerant MCLK input	–0.5 to AVDD + 2.5⁽⁴⁾
AMP_OUT_x to GND		22⁽³⁾	V
BSTRP_x to GND		29⁽³⁾	V
Operating free-air temperature		0 to 85	°C
Storage temperature range, T_stg		–40 to 125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.

(2) 5-V tolerant inputs are PDN, RST, SCLK, LRCK, MCLK, SDIN, SDA, and SCL.

(3) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.

(4) Maximum pin voltage should not exceed 6 V.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
DVDD, AVDD	Digital, analog supply voltage		3	3.3	3.6	V
PVDD	Output power devices supply voltage		8		16.5⁽¹⁾⁽²⁾	V
V_IH	High-level input voltage	5-V tolerant	2			V
V_IL	Low-level input voltage	5-V tolerant			0.8	V
T_A	Operating ambient temperature range		0		85	°C
T_J ⁽²⁾	Operating junction temperature range		0		125	°C
R_L	Load impedance		4	8		Ω
R_L	Load impedance in PBTL		2			Ω
L_O	Output-filter inductance	Minimum output inductance under short-circuit condition	10			μH

(1) For operation at PVDD levels greater than 14.5 V, the modulation limit must be set to 96.1% or lower via the control port register 0x10.

(2) 16.5 V is the maximum recommended voltage for continuous operation of the TAS5733L device. Testing and characterization of the device is performed up to and including 16.5 V to ensure “in system” design margin. However, continuous operation at these levels is not recommended. Operation above the maximum recommended voltage may result in reduced performance, errant operation, and reduction in device reliability.

6.4 Thermal Characteristics

THERMAL METRIC⁽¹⁾		DCA (48 PINS)				UNITS
THERMAL METRIC⁽¹⁾		Special Test Case	JEDEC Standard 2-Layer PCB	JEDEC Standard 4-Layer PCB	TAS5733LEVM	UNITS
θ_JA	Junction-to-ambient thermal resistance⁽²⁾		50.7	27.6	25.0	°C/W
θ_JCtop	Junction-to-case (top) thermal resistance⁽³⁾	14.9		16.7		°C/W
θ_JB	Junction-to-board thermal resistance⁽⁴⁾	6.9		7.9		°C/W
ψ_JT	Junction-to-top characterization parameter⁽⁵⁾		1.2	0.8	0.7	°C/W
ψ_JB	Junction-to-board characterization parameter⁽⁶⁾		11.8	7.8	5.8	°C/W
θ_JCbot	Junction-to-case (bottom) thermal resistance⁽⁷⁾	1.7		2.2		°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.5 Electrical Characteristics

T_A = 25°, PVDD_x = 12 V, DVDD = AVDD = 3.3 V, R_L= 8 Ω, BTL BD mode, f_S = 48 kHz (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	ADR/FAULT and SDA	I_OH = –4 mA DVDD = AVDD = 3 V	2.4			V
V_OL	Low-level output voltage	ADR/FAULT and SDA	I_OL = 4 mA DVDD = AVDD = 3 V			0.5	V
I_IL	Low-level input current	Digital Inputs	V_I < V_IL DVDD = AVDD = 3.6 V			75	μA
I_IH	High-level input current	Digital Inputs	V_I > V_IH DVDD = AVDD = 3.6 V			75	μA
I_DD	3.3-V supply current	3.3-V supply voltage (DVDD, AVDD)	Normal mode		49	68	mA
I_DD	3.3-V supply current	3.3-V supply voltage (DVDD, AVDD)	Reset (RST = low, PDN = high)		23	38	mA

6.6 Speaker Amplifier Characteristics

PVDD = 12 V, BTL BD mode, AVDD = DVDD = 3.3 V, f_S = 48 KHz, R_L = 8 Ω, audio frequency = 1 kHz, AES17 filter, f_PWM = 384 kHz, T_A = 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions and as tested on the TAS5733L EVM.

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
P_O	Power output per channel	PVDD = 12 V, 10% THD, 1-kHz input signal		10		W
		PVDD = 12 V, 7% THD, 1-kHz input signal		9
		PVDD = 12 V, 1% THD, 1-kHz input signal		7.5
		PVDD = 13.2 V, 10% THD, 1-kHz input signal		12
		PVDD = 13.2 V, 7% THD, 1-kHz input signal		11
		PVDD = 13.2 V, 1% THD, 1-kHz input signal		9
THD+N	Total harmonic distortion + noise	PVDD = 12 V, P_O = 1 W		0.25		%
THD+N	Total harmonic distortion + noise	PVDD = 13.2 V, P_O = 1 W		0.3		%
V_n	Output integrated noise (rms)	A-weighted		30		μV
	Crosstalk	P_O = 1 W, f = 1 kHz (BD Mode), PVDD = 12 V		–79		dB
	Crosstalk	P_O =1 W, f = 1 kHz (AD Mode), PVDD = 12 V		–62		dB
	Output switching frequency	11.025, 22.05, 44.1-kHz data rate ±2%		288		kHz
	Output switching frequency	48, 24, 12, 8, 16, 32-kHz data rate ±2%		384		kHz
I_PVDD	Supply current	No load (PVDD)	Normal mode	16	25	mA
I_PVDD	Supply current	No load (PVDD)	Reset (RST = low, PDN = high)	3	8	mA
r_DS(on)⁽¹⁾	Drain-to-source resistance, low side	T_J = 25°C, includes metallization resistance		120		mΩ
r_DS(on)⁽¹⁾	Drain-to-source resistance, high side	T_J = 25°C, includes metallization resistance		120		mΩ
R_PD	Internal pulldown resistor at the output of each half-bridge	Connected when drivers are in the high-impedance state to provide bootstrap capacitor charge.		3		kΩ

(1) This does not include bond-wire or pin resistance.

6.7 Protection Characteristics

T_A = 25°, PVDD_x = 12 V, DVDD = AVDD = 3.3 V, R_L= 8 Ω, BTL BD mode, f_S = 48 kHz (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	UNIT
V_uvp(fall)	Undervoltage protection limit	PVDD falling	5.4	V
V_uvp(rise)	Undervoltage protection limit	PVDD rising	5.8	V
OTE	Overtemperature error		150	°C
I_OC	Overcurrent limit protection		4	A
I_OCT	Overcurrent response time		150	ns

6.8 Master Clock Characteristics⁽¹⁾

PVDD = 12 V, BTL BD mode, AVDD = DVDD = 3.3 V, f_S = 48 kHz, R_L = 8 Ω, audio frequency = 1 kHz, AES17 filter, f_PWM = 384 kHz, T_A = 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions (unless otherwise specified).

PARAMETER		MIN	TYP	MAX	UNIT
PLL INPUT PARAMETERS
f_MCLKI	MCLK frequency	2.8224		24.576	MHz
	MCLK duty cycle	40%	50%	60%
t_r / t_f(MCLK)	Rise/fall time for MCLK			5	ns

(1) For clocks related to the serial audio port, please see Serial Audio Port Timing Requirements.

6.9 I²C Interface Timing Requirements

		MIN	NOM	MAX
t_w(RST)	Pulse duration, RST active	100		μs
t_{d(I²C_ready)}	Time to enable I²C after RST goes high		13.5	ms
f_SCL	Frequency, SCL		400	kHz
t_w(H)	Pulse duration, SCL high	0.6		μs
t_w(L)	Pulse duration, SCL low	1.3		μs
t_r	Rise time, SCL and SDA		300	ns
t_f	Fall time, SCL and SDA		300	ns
t_su1	Setup time, SDA to SCL	100		ns
t_h1	Hold time, SCL to SDA	0		ns
t_(buf)	Bus free time between stop and start conditions	1.3		μs
t_su2	Setup time, SCL to start condition	0.6		μs
t_h2	Hold time, start condition to SCL	0.6		μs
t_su3	Setup time, SCL to stop condition	0.6		μs
C_L	Load capacitance for each bus line		400	pF

6.10 Serial Audio Port Timing Requirements

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_SCLKIN	Frequency, SCLK 32 × f_S, 48 × f_S, 64 × f_S	C_L ≤ 30 pF	1.024		12.288	MHz
t_su1	Setup time, LRCK to SCLK rising edge		10			ns
t_h1	Hold time, LRCK from SCLK rising edge		10			ns
t_su2	Setup time, SDIN to SCLK rising edge		10			ns
t_h2	Hold time, SDIN from SCLK rising edge		10			ns
	LRCK frequency		8	48	48	kHz
	SCLK duty cycle		40%	50%	60%
	LRCK duty cycle		40%	50%	60%
	SCLK rising edges between LRCK rising edges		32		64	SCLK edges
t_(edge)	LRCK clock edge with respect to the falling edge of SCLK		–1/4		1/4	SCLK period
t_r/t_f	Rise/fall time for SCLK/LRCK				8	ns
	LRCK allowable drift before LRCK reset				4	MCLKs

NOTE:

On power up, hold the TAS5733L RST LOW for at least 100 μs after DVDD has reached 3 V.

NOTE:

If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is deasserted (HIGH).

Figure 1. Reset Timing

Figure 2. SCL and SDA Timing

Figure 3. Start and Stop Conditions Timing

Figure 4. Serial Audio Port Timing

6.11 Typical Characteristics - Stereo BTL Mode

Figure 5. Output Power vs Supply Voltage - BTL

PVDD = 12 V

R_L = 8 Ω

Figure 7. THD+N vs Frequency - BTL

PVDD = 12 V

R_L = 4 Ω

Figure 9. THD+N vs Frequency - BTL

PVDD = 12 V

R_L = 6 Ω

Figure 11. THD+N vs Output Power - BTL

		R_L = 8 Ω
Total Output Power includes power delivered from both amplifier outputs. For instance, 40 W of total output power means 2 × 20 W, with 20 W delivered by one channel and 20 W delivered by the other channel.

Figure 13. Efficiency vs Total Output Power - BTL

PVDD = 12 V

R_L = 8 Ω

Figure 15. Crosstalk vs Frequency - BTL

Figure 6. Idle Channel Noise vs Supply Voltage - BTL

PVDD = 12 V

R_L = 6 Ω

Figure 8. THD+N vs Frequency - BTL

PVDD = 12 V

R_L = 8 Ω

Figure 10. THD+N vs Output Power - BTL

PVDD = 12 V

R_L = 4 Ω

Figure 12. THD+N vs Output Power - BTL

		R_L = 4 Ω
Total Output Power includes power delivered from both amplifier outputs. For instance, 40 W of total output power means 2 × 20 W, with 20 W delivered by one channel and 20 W delivered by the other channel.

Figure 14. Efficiency vs Total Output Power - BTL

PVDD = 12 V

R_L = 4 Ω

Figure 16. Crosstalk vs Frequency - BTL

6.12 Typical Characteristics - Mono PBTL Mode

PVDD = 12 V

R_L = 4 Ω

Figure 17. THD+N vs Frequency - PBTL

PVDD = 12 V

R_L = 2 Ω

Figure 19. THD+N vs Frequency - PBTL

PVDD = 12 V

R_L = 3 Ω

Figure 21. THD+N vs Output Power - PBTL

Figure 23. Output Power vs PVDD - PBTL

	R_L = 2 Ω
Total Output Power includes power delivered from both amplifier outputs. For instance, 40 W of total output power means 2 × 20 W, with 20 W delivered by one channel and 20 W delivered by the other channel.

Figure 25. Efficiency vs Output Power - PBTL

PVDD = 12 V

R_L = 3 Ω

Figure 18. THD+N vs Frequency - PBTL

PVDD = 12 V

R_L = 4 Ω

Figure 20. THD+N vs Output Power - PBTL

PVDD = 12 V

R_L = 2 Ω

Figure 22. THD+N vs Output Power - PBTL

	R_L = 4 Ω
Total Output Power includes power delivered from both amplifier outputs. For instance, 40 W of total output power means 2 × 20 W, with 20 W delivered by one channel and 20 W delivered by the other channel.

Figure 24. Efficiency vs Output Power - PBTL

Figure 26. Idle Channel Noise vs PVDD - PBTL

封裝選項

機械數據 (封裝 | 引腳)

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Characteristics

6.5 Electrical Characteristics

6.6 Speaker Amplifier Characteristics

6.7 Protection Characteristics

6.8 Master Clock Characteristics(1)

6.9 I²C Interface Timing Requirements

6.10 Serial Audio Port Timing Requirements

6.11 Typical Characteristics - Stereo BTL Mode

6.12 Typical Characteristics - Mono PBTL Mode

6.8 Master Clock Characteristics⁽¹⁾