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SLOS670B November 2010 – December 2016 TAS5727

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PHP|48
- MPQF051B

散熱焊盤機械數據 (封裝 | 引腳)

PHP|48
- PPTD101G

訂購信息

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	DVDD, AVDD	–0.3	3.6	V
Supply voltage	PVDD_x	–0.3	30	V
Input voltage	3.3-V digital input	–0.5	DVDD + 0.5	V
	5-V tolerant⁽²⁾ digital input (except MCLK)	–0.5	DVDD + 2.5⁽⁴⁾
	5-V tolerant MCLK input	–0.5	AVDD + 2.5⁽⁴⁾
OUT_x to PGND_x			32⁽³⁾	V
BST_x to PGND_x			43⁽³⁾	V
Input clamp current, I_IK			±20	mA
Output clamp current, I_OK			±20	mA
Operating free-air temperature		0	85	°C
Operating junction temperature		0	150	°C
Storage temperature, T_stg		–40	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.

(2) 5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.

(3) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.

(4) Maximum pin voltage should not exceed 6 V.

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
	Digital/analog supply voltage	DVDD, AVDD	3	3.3	3.6	V
	Half-bridge supply voltage	PVDD_x ⁽¹⁾	8		26	V
V_IH	High-level input voltage	5-V tolerant	2			V
V_IL	Low-level input voltage	5-V tolerant			0.8	V
T_A	Operating ambient temperature		0		85	°C
T_J⁽²⁾	Operating junction temperature		0		125	°C
R_L (BTL)	Load impedance	Output filter: L = 15 μH, C = 680 nF	4	8		Ω
R_L (PBTL)	Load impedance	Output filter: L = 15 μH, C = 680 nF	2	4		Ω
L_O (BTL)	Output-filter inductance	Minimum output inductance under short-circuit condition	10			μH
	Output sample rate	11.025/22.05/44.1-kHz data rate ±2%		288		kHz
	Output sample rate	48/24/12/8/16/32-kHz data rate ±2%		384		kHz

(1) For operation at PVDD_x levels greater than 18 V, the modulation limit must be set to 93.8% through the control port register 0x10.

(2) Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		TAS5727	UNIT
		PHP (HTQFP)
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	27.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	13	°C/W
R_θJB	Junction-to-board thermal resistance	1.1	°C/W
ψ_JT	Junction-to-top characterization parameter	20.7	°C/W
ψ_JB	Junction-to-board characterization parameter	0.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	6.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

8.5 DC Electrical Characteristics

T_A = 25°, PVCC_x = 18 V, DVDD = AVDD = 3.3 V, R_L= 8 Ω, BTL AD mode, f_S = 48 kHz (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	A_SEL_FAULT and SDA	I_OH = –4 mA DVDD = 3 V	2.4			V
V_OL	Low-level output voltage	A_SEL_FAULT and SDA	I_OL = 4 mA DVDD = 3 V			0.5	V
I_IL	Low-level input current		V_I < V_IL ; DVDD = AVDD = 3.6 V			75	μA
I_IH	High-level input current		V_I > V_IH ; DVDD = AVDD = 3.6 V			75⁽³⁾	μA
I_DD	3.3-V supply current	3.3-V supply voltage (DVDD, AVDD)	Normal mode		49	68	mA
I_DD	3.3-V supply current	3.3-V supply voltage (DVDD, AVDD)	Reset (RESET = low, PDN = high)		23	38	mA
I_PVDD	Supply current	No load (PVDD_x)	Normal mode		32	50	mA
I_PVDD	Supply current	No load (PVDD_x)	Reset (RESET = low, PDN = high)		3	8	mA
r_DS(on) ⁽²⁾	Drain-to-source resistance, LS	T_J = 25°C, includes metallization resistance			75		mΩ
r_DS(on) ⁽²⁾	Drain-to-source resistance, HS	T_J = 25°C, includes metallization resistance			75		mΩ
I/O Protection
V_uvp	Undervoltage protection limit	PVDD falling			7.2		V
V_uvp,hyst	Undervoltage protection limit	PVDD rising			7.6		V
OTE⁽¹⁾	Overtemperature error				150		°C
OTE_HYST ⁽¹⁾	Extra temperature drop required to recover from error				30		°C
I_OC	Overcurrent limit protection				4.5		A
I_OCT	Overcurrent response time				150		ns
R_PD	Internal pulldown resistor at the output of each half-bridge	Connected when drivers are in the high-impedance state to provide bootstrap capacitor charge.			3		kΩ

(1) Specified by design

(2) This does not include bond-wire or pin resistance.

(3) I_IH for the PBTL pin has a maximum limit of 200 µA due to an internal pulldown on the pin.

8.6 AC Electrical Characteristics (BTL, PBTL)

PVDD_x = 18 V, BTL AD mode, f_S = 48 KHz, R_L = 8 Ω, R_OCP = 22 kΩ, C_BST = 33 nF, audio frequency = 1 kHz, AES17 filter,
f_PWM = 384 kHz, T_A = 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions (unless otherwise specified).

PARAMETER		TEST CONDITIONS	TYP	UNIT
P_O	Power output per channel	PVDD = 18 V,10% THD, 1-kHz input signal	21.5	W
		PVDD = 18 V, 7% THD, 1-kHz input signal	20.3
		PVDD = 12 V, 10% THD, 1-kHz input signal	9.6
		PVDD = 12 V, 7% THD, 1-kHz input signal	9.1
		PVDD = 8 V, 10% THD, 1-kHz input signal	4.2
		PVDD = 8 V, 7% THD, 1-kHz input signal	4
		PBTL mode, PVDD = 12 V, R_L = 4 Ω, 10% THD, 1-kHz input signal	18.7
		PBTL mode, PVDD = 12 V, R_L = 4 Ω, 7% THD, 1-kHz input signal	17.7
		PBTL mode, PVDD = 18 V, R_L = 4 Ω, 10% THD, 1-kHz input signal	41.5
		PBTL mode, PVDD = 18 V, R_L = 4 Ω, 7% THD, 1-kHz input signal	39
THD+N	Total harmonic distortion + noise	PVDD = 18 V, P_O = 1 W	0.07%
		PVDD = 12 V, P_O = 1 W	0.03%
		PVDD = 8 V, P_O = 1 W	0.1%
V_n	Output integrated noise (rms)	A-weighted	56	μV
	Crosstalk	P_O = 0.25 W, f = 1 kHz (BD Mode)	–82	dB
	Crosstalk	P_O = 0.25 W, f = 1 kHz (AD Mode)	–69	dB
SNR	Signal-to-noise ratio⁽¹⁾	A-weighted, f = 1 kHz, maximum power at THD < 1%	106	dB

(1) SNR is calculated relative to 0-dBFS input level.

8.7 PLL Input Parameters and External Filter Components

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_MCLKI	MCLK frequency		2.8224		24.576	MHz
	MCLK duty cycle		40%	50%	60%
t_r / t_f(MCLK)	Rise/fall time for MCLK				5	ns
	LRCLK allowable drift before LRCLK reset				4	MCLKs
	External PLL filter capacitor C1	SMD 0603 X7R		47		nF
	External PLL filter capacitor C2	SMD 0603 X7R		4.7		nF
	External PLL filter resistor R	SMD 0603, metal film		470		Ω

8.8 Serial Audio Ports Slave Mode

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
f_SCLKIN	Frequency, SCLK 32 × f_S, 48 × f_S, 64 × f_S	C_L = 30 pF	1.024		12.288	MHz
t_su1	Setup time, LRCLK to SCLK rising edge		10			ns
t_h1	Hold time, LRCLK from SCLK rising edge		10			ns
t_su2	Setup time, SDIN to SCLK rising edge		10			ns
t_h2	Hold time, SDIN from SCLK rising edge		10			ns
	LRCLK frequency		8	48	48	kHz
	SCLK duty cycle		40%	50%	60%
	LRCLK duty cycle		40%	50%	60%
	SCLK rising edges between LRCLK rising edges		32		64	SCLK edges
t_(edge)	LRCLK clock edge with respect to the falling edge of SCLK		–1/4		1/4	SCLK period
t_r/t_f	Rise/fall time for SCLK/LRCLK				8	ns

8.9 I²C Serial Control Port Operation

Timing characteristics for I²C Interface signals over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
f_SCL	Frequency, SCL	No wait states		400	kHz
t_w(H)	Pulse duration, SCL high		0.6		μs
t_w(L)	Pulse duration, SCL low		1.3		μs
t_r	Rise time, SCL and SDA			300	ns
t_f	Fall time, SCL and SDA			300	ns
t_su1	Setup time, SDA to SCL		100		ns
t_h1	Hold time, SCL to SDA		0		ns
t_(buf)	Bus free time between stop and start conditions		1.3		μs
t_su2	Setup time, SCL to start condition		0.6		μs
t_h2	Hold time, start condition to SCL		0.6		μs
t_su3	Setup time, SCL to stop condition		0.6		μs
C_L	Load capacitance for each bus line			400	pF

8.10 Reset Timing (RESET)

Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals.

PARAMETER		MIN	NOM	MAX	UNIT
t_w(RESET)	Pulse duration, RESET active	100			μs
t_{d(I2C_ready)}	Time to enable I²C			12	ms

Figure 1. Slave-Mode Serial Data-Interface Timing

Figure 2. SCL and SDA Timing

Figure 3. Start and Stop Conditions Timing

NOTES:

On power up, TI recommends that the TAS5727 RESET be held LOW for at least 100 μs after DVDD has reached 3 V.
If RESET is asserted LOW while PDN is LOW, then RESET must continue to be held LOW for at least 100 μs after PDN is deasserted (HIGH).

Figure 4. Reset Timing