ZHCSET5B May 2015 – February 2016 TAS5720L , TAS5720M
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Applications and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
5 Pin Configuration and Functions
RSM Package
VQFN 32 PINS
Top View
Pin Functions
| PIN | I/O/P(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ADR1 | 12 | I | I2C address inputs. Each pin can detect a short to DVDD, a short to GND, a 22-kΩ connection to GND, and a 22-kΩ connection to DVDD. |
| ADR0 | 13 | I | |
| AVDD | 28 | P | Analog power supply input. Connect directly to PVDD. |
| BST_N | 18 | P | Class-D Amplifier negative bootstrap. Connect to a capacitor between BST_N and OUT_N. |
| BST_P | 23 | P | Class-D Amplifier positive bootstrap. Connect to a capacitor between BST_P and OUT_P. |
| DVDD | 11 | P | Digital power supply. Connect to a 3.3-V supply with external decoupling capacitor. |
| FAULTZ | 2 | O | Open drain active low fault flag. Pull up on PCB with resistor to DVDD. |
| LRCLK | 4 | I | TDM interface frame synchronization. |
| GND | 10 | P | Ground. Connect to PCB ground plane. |
| 29 | |||
| GVDD | 30 | O | Class-D amplifier gate drive regulator output. Connect decoupling cap to PCB ground plane. |
| MCLK | 5 | I | Device master clock. |
| PGND | 19 | P | Power ground. Connect to PCB ground plane. |
| 20 | |||
| 21 | |||
| 22 | |||
| PVDD | 14 | P | Class-D amplifier power supply input. Connect to PVDD supply and decouple externally. |
| 15 | |||
| 26 | |||
| 27 | |||
| OUT_N | 16 | O | Class-D amplifier negative output. |
| 17 | |||
| OUT_P | 24 | O | Class-D amplifier positive output. |
| 25 | |||
| BCLK | 6 | I | TDM Interface serial bit clock. |
| SCL | 8 | I | I2C clock Input. Pull up on PCB with a 2.4-kΩ resistor. |
| SDA | 9 | I/O | I2C bi-directional data. Pull up on PCB with a 2.4-kΩ resistor. |
| SDIN | 7 | I | TDM interface data input. |
| SDZ | 3 | I | Active low shutdown signal. Assert low to hold device inactive. |
| Thermal Pad | 33 | G | Connect to GND for best system performance. If not connected to GND, leave floating. |
| VCOM | 32 | O | Common mode reference output. Connect decoupling capacitor to the VREF_N pin. |
| VREF_N | 1 | P | Negative reference for analog. Connect to VCOM and VREG capacitor negative pins. |
| VREG | 31 | O | Analog regulator output. Connect decoupling capacitor to the VREF_N pin. |
(1) I = input, O = output, P = power, I/O = bi-directional