ZHCSL71A April 2020 – July 2020 TAS5431-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
6.7 Typical Characteristics
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W per channel, AES17 filter, 1-kHz input, default I2C settings (unless otherwise noted)
| f(SW) = 400 kHz | TA = 25°C | V(PVDD) = 14.4 V |
