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ZHCSE68A August 2015 – October 2015 TAS5404-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PHD|64
- MPQF047F

散熱焊盤機械數據 (封裝 | 引腳)

PHD|64
- PPTD077I

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽³⁾

			MIN	MAX	UNIT
PVDD	DC supply voltage range	Relative to GND	–0.3	18	V
PVDD_MAX	DC supply voltage range	t ≤ 60 s exposure	–0.3	30	V
PVDD_PULSED	Pulsed supply voltage range	t ≤ 100 ms exposure	–1	50	V
PVDD_RAMP	Supply voltage ramp rate			15	V/ms
I_PVDD	Externally imposed dc supply current per PVDD or GND pin			±12	A
I_{PVDD_MAX}	Pulsed supply current per PVDD pin (one shot)	t < 100 ms		17	A
I_O	Maximum allowed DC current per output pin			±13.5	A
I_{O_MAX}⁽¹⁾	Pulsed output current per output pin (single pulse)	t < 100 ms		±17	A
I_{IN_MAX}	Maximum current, all digital and analog input pins⁽²⁾	DC or pulsed		±1	mA
I_{MUTE_MAX}	Maximum current on MUTE pin	DC or pulsed		±20	mA
I_{IN_ODMAX}	Maximum sink current for open-drain pins			7	mA
V_LOGIC	Input voltage range for pin relative to GND (SCL, SDA, I2C_ADDR pins)	Supply voltage range: 6 V < PVDD < 18 V	–0.3	6	V
V_MUTE	Voltage range for MUTE pin relative to GND	Supply voltage range: 6 V < PVDD < 18 V	–0.3	7.5	V
V_STANDBY	Input voltage range for STANDBY pin	Supply voltage range: 6 V < PVDD < 18 V	–0.3	5.5	V
V_{OSC_SYNC}	Input voltage range for OSC_SYNC pin relative to GND	Supply voltage range: 6 V < PVDD < 18 V	–0.3	3.6	V
V_GND	Maximum voltage between GND pins			±0.3	V
V_{AIN_AC_MAX}	Maximum ac-coupled input voltage⁽²⁾, analog input pins	Supply voltage range: 6 V < PVDD < 18 V		1.9	Vrms
T_J	Maximum operating junction temperature range		–55	150	°C
T_stg	Storage temperature		–55	150	°C

(1) Pulsed current ratings are maximum survivable currents externally applied to the TAS5404-Q1 device. The TAS5404-Q1 device can encounter high currents during reverse-battery, fortuitous open-ground, and fortuitous open-supply fault conditions.

(2) See the Application Information section for information on analog input voltage and ac coupling.

(3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum- rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾		±2500	V
		Charged device model (CDM), per AEC Q100-011 PHD Package	Corner pins excluding SCL	±750	V
			All pins (including SCL) except CP and CP_Top	±600
			CP and CP_Top pins	±400

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions⁽¹⁾

			MIN	NOM	MAX	UNIT
PVDD_OP	DC supply voltage range relative to GND		6	14.4	18	V
V_AIN⁽²⁾	Analog audio input signal level (TAS5414C-Q1)	AC-coupled input voltage	0		0.25–1⁽³⁾	Vrms
T_A	Ambient temperature		–40		105	°C
T_J	Junction temperature	An adequate heat sink is required to keep T_J within specified range.	–40		115	°C
R_L	Nominal speaker load impedance		2	4		Ω
V_PU	Pullup voltage supply (for open-drain logic outputs)		3	3.3 or 5	5.5	V
R_{PU_EXT}	External pullup resistor on open-drain logic outputs	Resistor connected between open-drain logic output and V_PU supply	10		50	kΩ
R_{PU_I2C}	I²C pullup resistance on SDA and SCL pins		1	4.7	10	kΩ
R_{I2C_ADD}	Total resistance of voltage divider for I²C address slave 1 or slave 2, connected between D_BYP and GND pins		10		50	kΩ
R_REXT	External resistance on REXT pin	1% tolerance required	19.8	20	20.2	kΩ
C_{D_BYP} , C_{A_BYP}	External capacitance on D_BYP and A_BYP pins		10		120	nF
C_OUT	External capacitance to GND on OUT_X pins			150	680	nF
C_IN	External capacitance to analog input pin in series with input signal			0.47		μF
C_FLY	Flying capacitor on charge pump		0.47	1	1.5	μF
C_P	Charge pump capacitor	50 V required for load dump	0.47	1	1.5	μF
C_MUTE	MUTE pin capacitor		100	220	1000	nF
C_{OSCSYNC_MAX}	Allowed loading capacitance on OSC_SYNC pin			75		pF

(1) The Recommended Operating Conditions table specifies only that the TAS5404-Q1 device is functional in the given range. See the Electrical Characteristics table for specified performance limits.

(2) Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB

(3) Maximum recommended input voltage is determined by the gain setting.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TAS5404-Q1	UNIT
R_θJC	Junction-to-case (heat slug) thermal resistance	1.2	°C/W
R_θJA	Junction-to-ambient thermal resistance	This TAS5404-Q1 device is not intended to be used without a heatsink. Therefore, R_θJA is not specified. Refer to the Thermal Consideration section.

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Test conditions (unless otherwise noted): T_Case = 25°C, PVDD = 14.4 V, R_L = 4 Ω, f_S = 417 kHz, P_out = 1 W/ch, Rext = 20 kΩ, AES17 filter, default I²C settings, master-mode operation (see Figure 20)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OPERATING CURRENT
I_{PVDD_IDLE}	PVDD idle current	All four channels in MUTE mode		170	220	mA
I_{PVDD_Hi-Z}	PVDD idle current	All four channels in Hi-Z mode		93		mA
I_{PVDD_STBY}	PVDD standby current	STANDBY mode, T_J ≤ 85°C		2	10	μA
OUTPUT POWER
P_OUT	Output power per channel	4 Ω, THD+N ≤ 1%, 1 kHz, T_c = 75°C		20		W
		4 Ω, THD+N = 10%, 1 kHz, T_c = 75°C	25	26
		4 Ω, square wave, 1 kHz, T_c = 75°C		43
		2 Ω, THD+N = 1%, 1 kHz, T_c = 75°C		38
		2 Ω, THD+N = 10%, 1 kHz, T_c = 75°C	40	45
		2 Ω, square wave, 1 kHz, T_c = 75°C		70
EFF_P	Power efficiency	4 channels operating, 20-W output power/ch, L = 10 μH, T_J ≤ 85°C		90%
AUDIO PERFORMANCE
V_NOISE	Noise voltage at output	Zero input, and A-weighting		60	100	μV
	Channel crosstalk	P = 1 W, f = 1 kHz, enhanced crosstalk enabled through I²C (reg. 0x10)	70	85		dB
CMRR₅₄₂₄	Common-mode rejection ratio (TAS5424C-Q1)	f = 1 kHz, 1 Vrms referenced to GND, G = 26 dB	60	75		dB
PSRR	Power-supply rejection ratio	PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz	60	75		dB
THD+N	Total harmonic distortion + noise	P = 1 W, f = 1 kHz		0.02%	0.1%
f_S	Switching frequency	Switching frequency selectable for AM interference avoidance	336	357	378	kHz
			392	417	442
			470	500	530
R_AIN	Analog input resistance	Internal shunt resistance on each input pin	63	85	106	kΩ
V_{IN_CM}	Common-mode input voltage	AC-coupled common-mode input voltage (zero differential input)		1.3		Vrms
V_{CM_INT}	Internal common-mode input bias voltage	Internal bias applied to IN_M pin		3.3		V
G	Voltage gain (V_O/V_IN)	Source impedance = 0 Ω, gain measurement taken at 1 W of power per channel	11	12	13	dB
			19	20	21
			25	26	27
			31	32	33
G_CH	Channel-to-channel variation	Any gain commanded	–1	0	1	dB
PWM OUTPUT STAGE
R_DS(on)	FET drain-to-source resistance	Not including bond wire resistance, T_J = 25°C		65	90	mΩ
V_{O_OFFSET}	Output offset voltage	Zero input signal, G = 26 dB		±10	±50	mV
PVDD OVERVOLTAGE (OV) PROTECTION
V_{OV_SET}	PVDD overvoltage shutdown set		24.6	26.4	28.2	V
V_{OV_CLEAR}	PVDD overvoltage shutdown clear		24.4	25.9	27.4	V
PVDD UNDERVOLTAGE (UV) PROTECTION
V_{UV_SET}	PVDD undervoltage shutdown set		4.9	5.3	5.5	V
V_{UV_CLEAR}	PVDD undervoltage shutdown clear		6.2	6.6	6.9	V
AVDD
V_{A_BYP}	A_BYP pin voltage			6.5		V
V_{A_BYP_UV_SET}	A_BYP UV voltage			4.8		V
V_{A_BYP_UV_CLEAR}	Recovery voltage A_BYP UV			5.3		V
DVDD
V_{D_BYP}	D_BYP pin voltage			3.3		V
POWER-ON RESET (POR)
V_POR	PVDD voltage for POR	I²C active above this voltage			4	V
V_{POR_HY}	PVDD recovery hysteresis voltage for POR			0.1		V
REXT
V_REXT	Rext pin voltage			1.27		V
CHARGE PUMP (CP)
V_{CPUV_SET}	CP undervoltage			4.8		V
V_{CPUV_CLEAR}	Recovery voltage for CP UV			4.9		V
OVERTEMPERATURE (OT) PROTECTION
T_{OTW1_CLEAR}	Junction temperature for overtemperature warning		96	112	128	°C
T_{OTW1_SET} / T_{OTW2_CLEAR}			106	122	138	°C
T_{OTW2_SET} / T_{OTW3_CLEAR}			116	132	148	°C
T_{OTW3_SET} / T_{OTSD_CLEAR}			126	142	158	°C
T_OTSD	Junction temperature for overtemperature shutdown		136	152	168	°C
T_FB	Junction temperature for overtemperature foldback	Per channel	130	150	170	°C
CURRENT LIMITING PROTECTION
I_LIM	Current limit (load current)		8.5			A
OVERCURRENT (OC) SHUTDOWN PROTECTION
I_MAX	Maximum current (peak output current)	Any short to supply, ground, or other channels	9.8			A
TWEETER DETECT
I_{TH_TW}	Load-current threshold for tweeter detect		330	445	560	mA
I_{LIM_TW}	Load-current limit for tweeter detect			2.1		A
STANDBY MODE
V_IH	STANDBY input voltage for logic-level high	?	2			V
V_IL	STANDBY input voltage for logic-level low	?			0.7	V
I_STBY	STANDBY pin current			0.1	0.2	μA
MUTE MODE
G_MUTE	Output attenuation	MUTE pin ≤ 0.5 V for 200 ms or I²C Mute Enabled		100		dB
DC OFFSET DETECT
V_{TH_DC_TOL}	DC offset detect threshold tolerance			25%
t_DCD	DC offset detect step-response time for four channels				5.3	s
CLIP_OTW REPORT
V_{OH_CLIPOTW}	CLIP_OTW pin output voltage for logic level high (open-drain logic output)	External 47-kΩ pullup resistor to 3 V to 5.5 V	2.4			V
V_{OL_CLIPOTW}	CLIP_OTW pin output voltage for logic level low (open-drain logic output)	External 47-kΩ pullup resistor to 3 V to 5.5 V			0.5	V
t_{DELAY_CLIPDET}	CLIP_OTW signal delay when output clipping detected				20	μs
FAULT REPORT
V_{OH_FAULT}	FAULT pin output voltage for logic-level high (open-drain logic output)	External 47-kΩ pullup resistor to 3 V to 5.5 V	2.4			V
V_{OL_FAULT}	FAULT pin output voltage for logic-level low (open-drain logic output)	External 47-kΩ pullup resistor to 3 V to 5.5 V			0.5	V
OPEN, SHORT DIAGNOSTICS
R_S2P, R_S2G	Maximum resistance to detect a short from OUT pin(s) to PVDD or ground				200	Ω
R_{OPEN_LOAD}	Minimum load resistance to detect open circuit	Including speaker wires	300	740	1300	Ω
R_{SHORTED_LOAD}	Maximum load resistance to detect short circuit	Including speaker wires	0.5	1	1.5	Ω
I²C ADDRESS DECODER
t_{LATCH_I2CADDR}	Time delay to latch I²C address after POR			300		μs
V_{I2C_ADDR}	Voltage on I2C_ADDR pin for address 0	Connect to GND	0%	0%	15%	V_{D_BYP}
	Voltage on I2C_ADDR pin for address 1	External resistors in series between D_BYP and GND as a voltage divider	25%	35%	45%
	Voltage on I2C_ADDR pin for address 2		55%	65%	75%
	Voltage on I2C_ADDR pin for address 3	Connect to D_BYP	85%	100%	100%
I²C
t_{HOLD_I2C}	Power-on hold time before I²C communication	STANDBY high		1		ms
f_SCL	SCL clock frequency				400	kHz
V_IH	SCL pin input voltage for logic-level high	R_{PU_I2C} = 5-kΩ pullup, supply voltage = 3.3 V or 5 V	2.1		5.5	V
V_IL	SCL pin input voltage for logic-level low	R_{PU_I2C} = 5-kΩ pullup, supply voltage = 3.3 V or 5 V	–0.5		1.1	V
V_OH	SDA pin output voltage for logic-level high	I²C read, R_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V	2.4			V
V_O	SDA pin output voltage for logic-level low	I²C read, 3-mA sink current			0.4	V
V_IH	SDA pin input voltage for logic-level high	I²C write, R_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V	2.1		5.5	V
V_IL	SDA pin input voltage for logic-level low	I²C write, R_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V	–0.5		1.1	V
C _I	Capacitance for SCL and SDA pins				10	pF
OSCILLATOR
V_OH	OSC_SYNC pin output voltage for logic-level high	I2C_ADDR pin set to MASTER mode	2.4			V
V_OL	OSC_SYNC pin output voltage for logic-level low	I2C_ADDR pin set to MASTER mode			0.5	V
V_IH	OSC_SYNC pin input voltage for logic-level high	I2C_ADDR pin set to SLAVE mode	2			V
V_IL	OSC_SYNC pin input voltage for logic-level low	I2C_ADDR pin set to SLAVE mode			0.8	V
f_{OSC_SYNC}	OSC_SYNC pin clock frequency	I2C_ADDR pin set to MASTER mode, f_S = 500 kHz	3.76	4	4.24	MHz
		I2C_ADDR pin set to MASTER mode, f_S = 417 kHz	3.13	3.33	3.63
		I2C_ADDR pin set to MASTER mode, f_S = 357 kHz	2.68	2.85	3

7.6 Timing Requirements for I²C Interface Signals

over recommended operating conditions (unless otherwise noted)

		MIN	MAX	UNIT
t_r	Rise time for both SDA and SCL signals		300	ns
t_f	Fall time for both SDA and SCL signals		300	ns
t_w(H)	SCL pulse duration, high	0.6		μs
t_w(L)	SCL pulse duration, low	1.3		μs.
t_su(2)	Setup time for START condition	0.6		μs
t_h(2)	START condition hold time until generation of first clock pulse	0.6		μs
t_su(1)	Data setup time	100		ns
t_h(1)	Data hold time	0⁽¹⁾		ns
t_su(3)	Setup time for STOP condition	0.6		μs
C_B	Load capacitance for each bus line		400	pF

(1) The TAS5404-Q1 device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.