ZHCSN44B December 2021 – December 2023 SN75LVPE5421
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Secondary Mode | ||||||
| tSP | Pulse width of spikes which must be suppressed by the input filter |
50 | ns | |||
| tHD-STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated |
0.6 | μs | |||
| tLOW | LOW period of the SCL clock | 1.3 | μs | |||
| THIGH | HIGH period of the SCL clock | 0.6 | μs | |||
| tSU-STA | Set-up time for a repeated START condition |
0.6 | μs | |||
| tHD-DAT | Data hold time | 0 | μs | |||
| TSU-DAT | Data setup time | 0.1 | μs | |||
| tr | Rise time of both SDA and SCL signals | Pull-up resistor = 4.7 kΩ, Cb = 10pF | 120 | ns | ||
| tf | Fall time of both SDA and SCL signals | Pull-up resistor = 4.7 kΩ, Cb = 10pF | 2 | ns | ||
| tSU-STO | Set-up time for STOP condition | 0.6 | μs | |||
| tBUF | Bus free time between a STOP and START condition |
1.3 | μs | |||
| tVD-DAT | Data valid time | 0.9 | μs | |||
| tVD-ACK | Data valid acknowledge time | 0.9 | μs | |||
| Cb | Capacitive load for each bus line | 400 | pF | |||