10.1.1 Use Case of SNx5DP149

SNx5DP149 can be used on the motherboard and dongle applications. The following use case diagrams show the connection of DDC between source side and sink side. The control pin pull up and pull down resistors are shown from reference. If a high is needed only use the pull up. If a low is needed only use the pull down. If mid level is to be selected do not use either resistors and leave the pin floating/No connect. The 6.5-KΩ Vsadj resistor value shown is explained further in the compliance section.

Figure 28 shows the original connection of SNx5DP149 on motherboard through the DDC channel. The DDC DR default is 100-kHz and is capable to adjust to 400-kHz.

Figure 28. Implementation for Motherboard

shows the SNx5DP149 in the dongle application. It uses the unified structure on DisplayPort connector.

10.1.2 DDC Pullup Resistors

The pullup resistor value is determined by two requirements:

1. The maximum sink current of the I²C buffer:
   The maximum sink current is 3-mA or slightly higher for an I²C driver supporting standard-mode I²C^[4] operation.
Equation 1.
2. The maximum transition time on the bus:
   The maximum transition time, T, of an I²C bus is set by an RC time constant, where R is the pullup resistor value, and C is the total load capacitance. The parameter, k, can be calculated from Equation 3 by solving for t, the times at which certain voltage thresholds are reached. Different input threshold combinations introduce different values of t. Table 11 summarizes the possible values of k under different threshold combinations.
Equation 2.
Equation 3.

From Equation 1, R_up(min) = 5.5-V / 3-mA = 1.83-kΩ to operate the bus under a 5-V pullup voltage and provide less than 3-mA when the I²C device is driving the bus to a low state. If a higher sink current, for example 4 mA, is allowed, R_up(min) can be as low as 1.375-kΩ.

If DDC is working at a standard mode of 100-Kbps, the maximum transition time, T, is fixed, 1 μs, and using the k values from Table 11, the recommended maximum total resistance of the pullup resistors on an I²C bus can be calculated for different system setups. If DDC is working in a fast mode of 400-kbps, the transition time should be set at 300 ns, according to I²C^[4] specification.

To support the maximum load capacitance specified in the HDMI specification, C_cable(max) = 700-pF, C_source = 50-pF, C_i = 50-pF, and R_(max) can be calculated as shown in Table 12.

To accommodate the 3-mA drive current specification, a narrower threshold voltage range is required to support a maximum 800-pF load capacitance for a standard-mode I²C bus.

10.2.1 Design Requirements

The SNx5DP149 can be designed into many types of applications. All applications have certain requirements for the system to work properly. Two voltage rails are required to support the lowest possible power consumption. The OE pin must have a 0.1-µF capacitor to ground. This pin can be driven by a processor but the pin needs to change states after voltage rails have stabilized. Configure the device by using I²C. Pin strapping is provided as I²C is not available in all cases. Because sources may have different naming conventions, confirm the link between the source and the SNx5DP149 is correctly mapped. A swap function is provided for the input pins in case signaling is reversed between the source and the device. For the control pins the values provided below are when they are being controlled by a micro-controller. If this is not the case then using the 65-kΩ for a pull up for high, pulled down for low, and left floating for mid level.

10.2.2 Detailed Design Procedure

The SNx5DP149 is a signal conditioner that provides AC coupling to DC coupling level shifting, to support Dual Mode DisplayPort-capable GPUs or GPUs with AC-coupled drive capability to support HDMI or DVI connectors and compliance. Signal conditioning is accomplished using receive equalization, retiming, and output driver configurability. The transmitter drives 2 to 3 inches of board trace and connector.

Designing in the SNx5DP149 requires the following:

• Determine the loss profile between the GPU and the HDMI/DVI connector.
• Based upon the loss profile and signal swing, determine the optimal location for the SNx5DP149, to pass electrical compliance.
• Use the typical application drawings in Use Case of SNx5DP149 for information on using the AC coupling capacitors and control pin resistors.
• The DP149 has a receiver adaptive equalizer by default but can also be configured for fixed value equalization using the EQ_SEL control pin.
• Set the VOD, pre-emphasis, termination, and edge rate levels to support compliance by using the appropriate Vsadj resistor value and by setting the PRE_SEL and SLEW_CTL control pins.
• The thermal pad must be connected to ground.
• See the schematics in Application Information on recommended decouple capacitors from VCC pins to ground.

10.2.3 Application Curves

Figure 30. 4k2k30 TX Compliance Eye

Figure 31. 1080p TX Compliance Eye

10.3.1 Compliance Testing

Compliance testing is very system design specific. Properly designing the system and configuring the SNx5DP149 can help pass transmitter compliance for the system. The following information is the starting point to help prepare for compliance test. As each system is different there are many features in the DP149 to help tune the circuit. These include V_OD adjust by changing the Vsadj resistor value or using I²C. Other knobs to turn are pre/de-emphasis and slew rate control. Passing HDMI1.4b compliance is easier to accomplish when using I²C as this provides more fine tuning capability.

For the SNx5DP149RSB:

Pin Strapping

HDMI1.4b

Vsadj Resistor = 6.5 kΩ

PRE_SEL = L for –2 dB

SLEW_CTL = NC

I²C

HDMI1.4b

Vsadj Resistor = 6.5 kΩ

VSWING_DATA & VSWING_CLK to -7% = Reg0Ch[7:2] = 111111

PRE_SEL = Reg0Ch[1:0] = 00: (Labeled HDMI_TWPST)

TX_TERM_CTL: Reg0Bh[4:3]

• <2 Gbps = 00 for no termination (This may be best value for all HDMI1.4b)
• >2 Gbps and < 3.4 Gbps = 01 for 150 to 300 Ω

SLEW_CTL = Reg0Bh[7:6] = 10