Table 2. Packaging Options

7.3.1 Hot Plug Detect

The SN75DP139 has a built in level shifter for the HPD outputs. The output voltage level of the HPD pin is defined by the voltage level of the VCC pin. The HPD input or HPD_SINK side has 130kohm of pull down resistor integrated.

The logic of the HPD_SOURCE output always follows the logic state of the HPD_SINK input based on the HPDINV pin logic, regardless of whether the device is in Active or Low Power Mode

7.3.2 Aux / I²C Pins

The SN75DP139 utilizes an active I²C repeater. The repeater is designed to isolate the parasitic effects of the system in order to aid with system level compliance.

In addition to the I²C repeater, the SN75DP139 also supports the connector detection I²C register. This register is enabled via the I²C_EN pin. When active an internal memory register is readable via the AUX_I²C I/O. The functionality of this register block is described in the Programming section.

7.3.3 TMDS and Main Link Pins

The main link inputs are designed to support DisplayPort 1.1 specification. The TMDS outputs of the SN75DP139 are designed to support the Digital Video Interface (DVI) 1.0 and High Definition Multimedia Interface (HDMI) 1.4b specifications. The differential output voltage swing can be fine tuned with the R_Vsadj resistor.

The DP++ (dual-mode) input of the SN75DP139 is designed to accommodate the standard DP level ac coupled signal with no pre-emphasis with up to 16 inches of trace (4 mil 100 Ω differential stripline).

7.3.4 Input/Output Equivalent Circuits

Figure 21. DisplayPort Input Stage

Figure 22. TMDS Output Stage

Figure 23. HPD and Control Input Stage

Figure 24. HPD Output Stage

Figure 25. I²C Input and Output Stage

7.4.1 Active

The SN75DP139 activates the main link channel and thus is able to transmit the TMDS content.

7.4.2 Low Power With DDC Channel Enabled

The SN75DP139 is in low power but keeps its DDC channel active, this allows the device to configure its internal I2C registers.

7.4.3 Low Power

The SN75DP139 is in the lowest power mode, with no activity on the DDC or main link channels.

7.5.1 I²C Interface Notes

The I²C interface can be used to access the internal memory of the SN75DP139. I²C is a two-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The SN75DP139 works as a slave and supports the standard mode transfer (100 kbps) as defined in the I²C-Bus Specification.

The basic I²C start and stop access cycles are shown in Figure 26.

The basic access cycle consists of the following:

• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition

Figure 26. I²C Start And Stop Conditions

7.5.2 General I²C Protocol

• The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 28. All I²C-compatible devices should recognize a start condition.
• The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 27). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 28) by pulling the SDA line low during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a communication link with a slave has been established.
• The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary (See Figure 29).
• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 29). This releases the bus and stops the communication link with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address.

Figure 27. I²C Bit Transfer

Figure 28. I²C Acknowledge

Figure 29. I²C Address And Data Cycles

During a read cycle, the slave receiver will acknowledge the initial address byte if it decodes the address as its address. Following this initial acknowledge by the slave, the master device becomes a receiver and acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 30 and Figure 31. See Example – Reading from the SN75DP139 section for more information.

Figure 30. I²C Read Cycle

Figure 31. Multiple Byte Read Transfer

7.5.3 Slave Address

Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should comply with the I²C specification that ranges from 2kΩ to 19kΩ. When the bus is free, both lines are high. The address byte is the first byte received following the START condition from the master device. The 7-bit address is factory preset to 1000000. Table 3 lists the calls that the SN75DP139 will respond to.