ZHCSLJ9E October 1998 – July 2020 SN74LVCH32373A
PRODUCTION DATA
7.3.6 Bus-Hold Data Inputs
Each data input (D) on this device includes a weak latch that maintains a valid logic level on the input. The state of these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low state. After data has been sent through a channel, the latch then maintains the previous state on the input if the line is left floating. It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as it may cause undefined inputs to occur which can lead to excessive current consumption.
Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs application report explains the problems associated with leaving CMOS inputs floating. These latches remain active at all times, independent of all control signals such as direction control or output enable. The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.
Figure 7-2 Bus-Hold circuit block diagram representation