SCES201N April 1999 – September 2015 SN74LVC2G32
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DCU|8
- YZP|8
- DCT|8
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
1 Features
-
Available in the Texas Instruments
NanoFree™ Package - Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Maximum tpd of 3.8 ns at 3.3 V
- Low Power Consumption, 10-µA Maximum ICC
- ±24-mA Output Drive at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
- Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the VCC Level
- Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II - ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
2 Applications
- Down Translation
- Logical OR
3 Description
This dual 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G32 device performs the Boolean function 
in positive logic.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE |
|---|---|---|
| SN74LVC2G32DCT | SSOP (8) | 2.95 mm × 2.80 mm |
| SN74LVC2G32DCU | VSSOP (8) | 2.30 mm × 2.00 mm |
| SN74LVC2G32YZP | DSBGA (8) | 1.91 mm × 0.91 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Logic Diagram (Positive Logic)
