ZHCSM00N April 1999 – September 2020 SN74LVC2G126
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
The SN74LVC2G126 device contains a dual buffer gate with output enable control and performs the Boolean function Y = A.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.