SCES198N April 1999 – December 2015 SN74LVC2G08
PRODUCTION DATA.
- 1Features
- 2Applications
- 3Specifications
- 4Detailed Description
- 5Application and Implementation
- 6Power Supply Recommendations
- 7Layout
- 8Device and Documentation Support
- 9Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
1 Features
-
Available in the Texas Instruments
NanoStar™ and NanoFree™ Package - Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.7 ns at 3.3 V
- Low Power Consumption, 10-μA Maximum ICC
- ±24-mA Output Drive at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
- Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the VCC Level
- Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II - ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
2 Applications
- IP Phones: Wired and Wireless
- Optical Networking: EPON and Video Over Fiber
- Point-to-Point Microwave Backhaul
- Power: Telecom DC/DC Module: Analog
- Power: Telecom DC/DC Module: Digital
- Private Branch Exchange (PBX)
- Telecom Shelter: Power Distribution Unit (PDU)
- Vector Signal Analyzers and Generators
- Wireless Communications Testers
- Wireless Repeaters
- xDSL Modem/DSLAM
Description
This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G08 device performs the Boolean function 
in positive logic.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN74LVC2G08DCT | SM8 (8) | 2.95 mm × 2.80 mm |
| SN74LVC2G08DCU | VSSOP (8) | 2.30 mm × 2.00 mm |
| SN74LVC2G08YZP | DSBGA (8) | 1.91 mm × 0.91 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Logic Diagram (Positive Logic)
Revision History
Changes from M Revision (April 2014) to N Revision
- Added Pin Configuration and Functions section, ESD Ratings and Thermal Information tables, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go