ZHCSUV0J April 1999 – February 2024 SN74LV4066A
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
Figure 4-1 D or PW Package, 14-Pin SOIC or
TSSOP (Top View)
Figure 4-2 RGY Package, 14- Pin QFN (Top
View)| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| 1A | 1 | I/O | Input/Output to switch channel 1 |
| 1B | 2 | I/O | Input/Output to switch channel 1 |
| 2B | 3 | I/O | Input/Output to switch channel 2 |
| 2A | 4 | I/O | Input/Output to switch channel 2 |
| 2C | 5 | I | Control line for channel 2. Switch is ON when control pin is high. |
| 3C | 6 | I | Control line for channel 3. Switch is ON when control pin is high. |
| GND | 7 | — | Ground (0V) reference |
| 3A | 8 | I/O | Input/Output to switch channel 3 |
| 3B | 9 | I/O | Input/Output to switch channel 3 |
| 4B | 10 | I/O | Input/Output to switch channel 4 |
| 4A | 11 | I/O | Input/Output to switch channel 4 |
| 4C | 12 | I | Control line for channel 4. Switch is ON when control pin is high. |
| 1C | 13 | I | Control line for channel 1. Switch is ON when control pin is high. |
| VCC | 14 | — | Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1μF to 10μF between VDD and GND. |
| Thermal pad | — | It is recommended to tie the pad to GND for the best performance. | |