ZHCSWI9H August 2003 – October 2024 SN74LV4051A-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Thermal Information: SN74LV4051A-Q1
- 5.4 Recommended Operating Conditions
- 5.5 Electrical Characteristics
- 5.6 Timing Characteristics VCC = 2.5 V ± 0.2 V
- 5.7 Timing Characteristics VCC = 3.3 V ± 0.3 V
- 5.8 Timing Characteristics VCC = 5 V ± 0.5 V
- 5.9 AC Characteristics
- 6 Parameter Measurement Information
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- PW|16
- DYY|16
- DW|16
- D|16
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DW|16
訂購信息
4 Pin Configuration and Functions
Figure 4-1 D, PW or DYY Package, 16-Pin
SOIC, TSSOP, or SOT-23-THIN (Top View)Table 4-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| Y4 | 1 | I(2) | Input to mux |
| Y6 | 2 | I(2) | Input to mux |
| COM | 3 | O(2) | Output of mux |
| Y7 | 4 | I(2) | Input to mux |
| Y5 | 5 | I(2) | Input to mux |
| INH | 6 | I(2) | Enables the outputs of the device. Logic low level with turn the outputs on, high level will turn them off. |
| GND | 7 | — | Ground |
| GND | 8 | — | Ground |
| C | 9 | I | Selector line for outputs (see Section 7.4 for specific information) |
| B | 10 | I | Selector line for outputs (see Section 7.4 for specific information) |
| A | 11 | I | Selector line for outputs (see Section 7.4 for specific information) |
| Y3 | 12 | I(2) | Input to mux |
| Y0 | 13 | I(2) | Input to mux |
| Y1 | 14 | I(2) | Input to mux |
| Y2 | 15 | I(2) | Input to mux |
| Vcc | 16 | I | Device power input |
(1) I = input, O = output
(2) These I/O descriptions represent the device when used as a
multiplexer, when this device is operated as a demultiplexer pins Y0-Y7 may be
considered outputs (O) and the COM pin may be considered inputs (I).