ZHCSRV9E February 2001 – March 2023 SN74LV393A
PRODMIX
請參考 PDF 數據表獲取器件具體的封裝圖。
These devices comprise two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK) input. These devices change state on the negative-going transition of the CLK pulse. N-bit binary counters can be implemented with each package, providing the capability of divide by 256. The ’LV393A devices have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.